NDLI: An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform

Content Provider	IEEE Xplore Digital Library
Author	Jain, R. Panda, P.R.
Copyright Year	2007
Description	Author affiliation: IP Dev., CoWare India Pvt. Ltd., Noida (Jain, R.)
Abstract	The discrete wavelet transform (DWT) forms the core of the JPEG2000 image compression algorithm. JPEG2000 standard defines an irreversible DWT by a lifting scheme of factorized coefficients using (9, 7) Daubechies coefficients. The paper proposed optimizations on lifting based 1D-DWT data flow graph resulting in a new pipelining scheme, which is more power-efficient than existing approaches. The authors have shown that the constant multipliers defined by JPEG2000 standard, have latency of about 1.6 times the general adder latency. Hence, while finding the critical path, the basic assumption of multiplier latency being much greater than the adder latency does not hold for DWT in JPEG2000. How 75% multiplications can be reduced at the scaling step by this 2D-DWT implementation was also shown. This multiplication reduction not only saves power but also results in area saving by eliminating three multipliers in the hardware
Starting Page	1377
Ending Page	1380
File Size	344959
Page Count	4
File Format	PDF
ISBN	1424409209
DOI	10.1109/ISCAS.2007.378484
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Wavelet transforms Discrete wavelet transforms Transform coding Delay Buffer storage Image coding Hardware Computer architecture Registers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

Efficient Line-Based VLSI Architecture for 2-D Lifting DWT

Pipelined Lifting-Based VLSI Architecture for Two-Dimensional Inverse Discrete Wavelet Transform

High-Speed and Power Efficient Lifting-Based VLSI Architecture for Two-Dimesional Discrete Wavelet Transform

An efficient VLSI architecture for JPEG2000 encoder

An efficient line based VLSI architecture for 2D lifting DWT

Semi-recursive VLSI architecture for two dimensional discrete wavelet transform

A VLSI architecture for lifting-based wavelet transform

An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform

Similar Documents

An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

Efficient Line-Based VLSI Architecture for 2-D Lifting DWT

Pipelined Lifting-Based VLSI Architecture for Two-Dimensional Inverse Discrete Wavelet Transform

High-Speed and Power Efficient Lifting-Based VLSI Architecture for Two-Dimesional Discrete Wavelet Transform

An efficient VLSI architecture for JPEG2000 encoder

An efficient line based VLSI architecture for 2D lifting DWT

Semi-recursive VLSI architecture for two dimensional discrete wavelet transform

A VLSI architecture for lifting-based wavelet transform

An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform