Low-leakage SRAM Design with Dual Vt Transistors

Conference Proceedings

Reducing the sub-threshold and gate tunneling leakage of SRAM cells using dual-Vt and dual-tox assessment

Article

1 leakage minimization of sram cells in a dual-vt and dual-tox technology.

Article

Reducing the Sub-threshold and Gate-tunneling Leakage of Sram Cells Using Dual-Vt and Dual-Tox Assignment (2006)

Article

Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment

Article

Leakage power estimation & minimization in a 6t sram cell using dual vth, dual tox, & stacking techniques 1.

Article

Stability Analysis of a Novel Proposed Low Power 10T SRAM Cell for Write Operation

Article

Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment

Article

A stable and power efficient SRAM cell

Article