NDLI: On-Chip Substrate Noise Suppression Using Clock Randomization Methodology

Please wait, while we are loading the content...

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

2012 IEEE International Conference on Circuits and Systems (ICCAS)

2012 IEEE International Symposium on Circuits and Systems

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2009 IEEE International Symposium on Circuits and Systems

2008 IEEE International Symposium on Circuits and Systems

2007 IEEE International Symposium on Circuits and Systems

It's really a Lagniappe!!

Technical Program Co-Chairs' message

Conference Committee

Technical Program Committee

Review Committee Members

ISCAS 2007 Keynote Speakers

Tutorial 1: Integrated Biosensors

Tutorial 2: Satellite Navigation Receiver Design: GPS and Beyond

Tutorial 3: Design of Programmable Wireless Networks aka Cognitive Radios

Tutorial 4: Circuit Techniques for Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology

Tutorial 6: Design Challenges and Solutions for Nanoscale Memories

Tutorial 8: Wireless Sensor Networks: From Theory to Practice

Tutorial 12: Challenges and Opportunities of Digital Design in Nanoscale CMOS

Tutorial 13: Analog Circuit Design on Digital CMOS : Why it is difficult, and which ideas help?

Tutorial 14: Design of Digital Filters Satisfying Prescribed Specifications

ISCAS 2007 Special Sessions

Table of contents

A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF Receiver

On the modeling and the stability of continuous-time ΣΔ-Modulators

Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal Processing

A 1.2V 130μA 10-bit MOS-Only Log-Domain ΣΔ Modulator

Living and Dealing with RF Impairments in Communication Transceivers

3.9G Radio Reception with SC-FDMA Waveforms Under I/Q Imbalance

Blind I/Q Imbalance Compensation in Multipath Environments

On the Impact of I/Q Imbalance in Multi-Carrier Systems for Different Channel Scenarios

On the Joint Compensation of IQ Imbalances and Phase Noise in MIMO-OFDM Systems

Distributed Video Coding with Spatial Correlation Exploited Only at the Decoder

Peak Transform for Efficient Image Representation and Coding

Rate Control for Hierarchical B-picture Coding with Scaling-factors

Block-Interleaved Error-Resilient Entropy Coding

A Perceptual Coding Method based on the Luma Sensitivity Model

Fundamental Performance Limits in Lossy Polyphase Systems: Apparent Power and Optimal Compensation

Computing Criticality of Lines in Power Systems

Probability Distribution of Blackouts in Complex Power Networks

Analog Emulation of a Reconfigurable Tap Changing Transformer

Application of Two-Layered Tabu Search to Optimal Allocation of D-FACTS for Uncertain Wind Power Generation

Design and Optimization of a Capacitive Micromachined Ultrasonic Transducer Micro-Array for Near Field Sensing

A CMOS-Based Capacitive Sensor for Laboratory-On-Chips: Design and Experimental Results

Piezo-powered floating gate injector for self-powered fatigue monitoring in biomechanical implants

A novel current scaling active pixel sensor with correlated double sampling readout circuit for real time medical x-ray imaging

DSP implementation of a low-complexity algorithm for real-time automated vessel detection in images of the fundus of the human retina

A Novel Interference Supression Technique employing Complex Adaptive ICA for Time-Varying Channels in Diversity Wireless QAM Receivers

Adaptive IIR Filtering via a Recursive Total Instrumental Variable Algorithm

Generalized Blind Mismatch Correction for a Two-Channel Time-Interleaved ADC: Analytic Approach

An Adaptive Low Rank Algorithm for Semispherical Antenna Arrays

New Normalized LMS Algorithms Based on the Kalman Filter

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors

Non Return Mobile Logic Family

A Four-Resonant-Tunneling-Diode (4RTD) NAND/NOR Logic Gate

Synthesis of Finite State Machines with Magnetic Domain Wall Logic

A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs

Efficient Thermal Via Planning for Placement of 3D Integrated Circuits

Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard

Embedded Jitter Measurement of High-speed I/O Signals

GALS Based Shared Test Architecture for Embedded Memories

A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable Hardware

Real-Time Extraction of Maximally Stable Extremal Regions on an FPGA

Programmable Floating Gate FPAA Switches Are Not Dead Weight

Programmable Conductance Switches for FPAAs

An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and Computation

A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects

A Novel Tri-State Binary Phase Detector

Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links

A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane Communication

Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology

Generation of White Noise by Using Chaos in Practical Phase-Locked Loop Integrated Circuit Module

Reverse-Time Chaos from a Randomly Driven Filter

Switching Phase States of Chaotic Circuits Coupled by Time-Varying Resistor

ADCs, Chaos and TRNGs: a Generalized View Exploiting Markov Chain Lumpability Properties

Design of Multi-Directional Multi-Scroll Chaotic Attractors Based on Fractional Differential Systems

A Compact High Current Efficiency Low-Voltage MOS Transconductor with Nearly Constant Input Voltage Range

A Three-Stage Amplifier with Quenched Multipath Frequency Compensation for All Capacitive Loads

Low-Power Digitally Controlled CMOS Source Follower Variable Attenuator

Predictive Switched-Capacitor Track-and-Hold Amplifier with Improved Linearity

150 μA CMOS Transconductor with 82 dB SFDR

A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta Modulators

A DEM Scheme for I/Q Mismatch Compensation in Multi-Bit CT ΔΣ Modulator

Noise-Coupled Multi-Cell Delta-Sigma ADCs

Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma Modulators

Mixed-Order Sturdy MASH Δ-Σ Modulator

Carrier frequency synchronization for mobile television receivers

Efficient Transmitter Self-Calibration and Amplifier Linearization Techniques

Digital Compensation of Frequency Dependent Imperfections in Direct Conversion I-Q Modulators

Multipath Polyphase Circuits and their Application to RF Transceivers

Adaptive Pre-Distortion of Nonlinear Systems Using Out-of-Band Energy Minimization

A Universal Approach to Developing Fast Algorithm for Simplified Order-16 ICT

A PD Feed-back Rate Control Algorithm for Multiple Video Object Coding

On Model Parameter Estimation for H.264/AVC Rate Control

Chroma Coding Efficiency Improvement with Context Adaptive Lagrange Multiplier (CALM)

Image Compression using 2D Dual-tree Discrete Wavelet Transform (DDWT)

A PEEC approach for circular spiral inductive components modeling

An Integrated Switching Power Converter with a Hybrid Pulse-Train/PWM Control

Modeling the Substrate Noise Injected by a DC-DC Converter

Digital Inverse Timing Generator with Wide Dynamic Range

Design of Maximum-Efficiency Integrated Voltage Doubler

A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording Applications

An Experimental Study of Voltage, Current, and Charge Controlled Stimulation Front-End Circuitry

A New RF Radiometer for Absolute Noninvasive Temperature Sensing in Biomedical Applications

A 2.5-V 4-μW Low-Power Delta-Sigma Modulator for Implantable Cardiac Pacemaker with Periodic Bias Current Reduction Technique

A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier

Fast Basis Selection and Instantaneous Frequency Tracking for Audio Signal Analysis and Synthesis

Emotion Recognition Using Novel Speech Signal Features

An Identification Technique for Noisy ARMA Systems in Correlation Domain

Real-Time DSP Implementation of a Subband Beamforming Algorithm for Dual Microphone Speech Enhancement

Novel Non-linear Inverse Quantization Algorithm and its Architecture for Digital Audio Codecs

Fault Tolerance Analysis of NoC Architectures

Multiple Upsets Tolerance in SRAM Memory

A Miniaturized Delay Line based on Slow-Wave Substrates

Gigascale System Design of Sensor Networks for Active Volcanoes

Open Two-State Quantum Systems Solved by Harmonic Balance

Characterization of a Fault-tolerant NoC Router

Fast Fair Crossbar Scheduler for On-chip Router

Evaluation of Algorithms for Low Energy Mapping onto NoCs

An Information Theory Approach to Power - Optimal Trafic Routing in Networks on Chips

Binary-Truncated CDMA-Based On-Chip Network

Holographic memory reconfigurable VLSI

Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGA

Rapid C to FPGA Prototyping with Multithreaded Emulation Engine

Visualization of SystemC Designs

Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem Applications

A 0.18-μm CMOS Squarer Circuit for a Non-Coherent UWB Receiver

A Fully Integrated Concurrent Dual-Band Low Noise Amplifier with Suspended Inductors in SiGe 0.35 μm BiCMOS Technology

A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications

A Low-Power CMOS Low-IF Receiver Front-End for 2450-MHz Band IEEE 802.15.4 ZigBee Standard

A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers

The Composition Rule for Multivariate Volterra Operators and its Application to Circuit Analysis

Studying Nonlinear Dynamical Systems on a Reconfigurable Analog Platform

Per-Element Decompostion in Distortion Analysis

Modeling the Telephone Call Network

Novel Analysis of Phase Noise in Oscillators

Low-Voltage Linearly Tunable CMOS Transconductor with Common-Mode Feedforward

THD+Noise Estimation in Class-D Amplifiers

Two-Stage OTA Design Based on Settling-Time Constraints

A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS Resistor

A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter

A Segmented Data-Weighted-Averaging Technique

A Digital-Summing Feedforward Σ-Δ Modulator and its Application to a Cascade ADC

A 0.9mA 95dB ΣΔ Modulator for Digital RF Hearing Aid in 0.35μm CMOS

A Theoretical Analysis of Split Delta-Sigma ADCs

Discrete-Time Modeling of Clock Jitter in Continuous-Time ΔΣ Modulators

Algorithmic aspects in RF Circuit Simulation

Nonlinear, Transient Simulation of Distributed RF Circuits using Discrete-Time Convolution

An inverse method of characteristics for analyzing circuits with widely separated time-scales

Noise Analysis Problems and Techniques for RF Electronic Circuits and Optical Fiber Communication Systems

Multi-Time Method Based on State Equations for RF Circuit Analysis

A Comparative Study of Compensation Techniques in Directional DCT's

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine

Macroblock-level Reduced Resolution Video Coding Allowing Adaptive DCT Coefficients Selection

High-Accuracy and Low-Complexity Fixed-Point Inverse Discrete Cosine Transform Based on AAN's Fast Algortihm

Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients

Output Characteristics of Class E Amplifier With Nonlinear Shunt Capacitance Versus Supply Voltage

Dynamic Droop Scaling for Improving Current Sharing Performance in a System with Multiple Supplies

Designing an Accurate and Robust LC-Compliant Asynchronous ΣΔ Boost DC-DC Converter

Class DE Inverter with Asymmetric Shunt Capacitors

Power Harvesting With PZT Ceramics

Design Strategies for Multi-Channel Low-Noise Recording Systems

Wireless Stimulus-Reflex Detection for Neonatal Monitoring

Novel Charge-Metering Stimulus Amplifier for Biomimetic Implantable Prosthesis

Charge Balancing in Functional Electrical Stimulators: A Comparative Study

A 70dB Gain Low-Power Band-Pass Amplifier for Bio-Signals Sensing Applications

A Class of Cosine-Modulated Filter Banks with Multiple Prototype Filters

Design of Cosine-Modulated Pseudo-QMF Banks Using Semidefinite Programming Relaxation

Beamforming of Temporally-Broadband-Bandpass Plane Waves using Real Polyphase 2-D FIR Trapezoidal Filters

Filtering of Discrete Linear Repetitive Processes with H and l2-l Performance

Revisiting the Absolutely Minimal Realization for Two-dimensional Digital Filters

Sensor Integration in Autonomous Systems

A Systems View of a Neuromorphic VLSI Echolocation System

Integrating high-level sensor features via STDP for bio-inspired navigation

Sensor-based Dynamic Control of the Central Pattern Generator for Locomotion

Elastic Grid Based Analysis of Motion Field for Object-Motion Detection in Airborne Video Flows

Delay and Clock Skew Variation due to Coupling Capacitance and Inductance

Design of Reversible Sequential Elements With Feasibility of Transistor Implementation

Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs

Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops

Quasi-Resonant Interconnects: A Low Power Design Methodology

Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew

Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding

Wavelet-Based Interpolation Point Selection for Multi-Shifted Arnoldi

A Novel Active Decoupling Capacitor Design in 90nm CMOS

On the degree of MIMO systems

High Speed Sphere Decoding Based on Vertically Incremental Computation

Beamforming MIMO Receiver with Reduced Hardware Complexity

VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding

MIMO Transceiver Design Based on a Modified Geometric Mean Decomposition

Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control Circuit

Class AB Pseudo-Differential CMOS Squarer Circuit

Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map

From n-scroll to n×m-scroll attractors: A general structure based on Chua's circuit framework

Power Supply Noise in Bang-Bang Control Class D Amplifier

Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting Technique

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier

Highly Linear Bipolar Transconductor For Broadband High-Frequency Applications with Improved Input Voltage Swing

A New High-Speed Class-AB Current-Mode Circuit

On the Implicit Anti-Aliasing Feature of Continuous-Time Multistage Noise-Shaping Sigma-Delta Modulators

Design of a 130-nm CMOS Reconfigurable Cascade ΣΔ Modulator for GSM/UMTS/Bluetooth

Tonality Index of Sigma-Delta Modulators : A Psychoacoustics Model Based Approach

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

A 10-bit 2GHz Current-Steering CMOS D/A Converter

Design Considerations for Future RF Circuits

Receiver Front-End Circuits for Future Generations of Wireless Communications

Companding Baseband Switched Capacitor Filters and ADCs for WLAN Applications

Multifunctional RF Transmitters for Next Generation Wireless Transceivers

Low-Complexity Ultra Wideband Communications

Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding Framework

Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware

CREMA: A Parallel Hardware Raytracing Machine

A Real Time and Low Cost Hardware Architecture for Video Abstraction System

VLSI Implementation for Portable Application Oriented MPEG-4 Audio Codec

Adaptive Variable Switching Frequency Digital Controller Algorithm to Optimize Efficiency

Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters

Bifurcation of multiple-input parallel dc-dc converters with dynamic winner-take-all switching

Computer-Aided Average-Value Modeling of Fourth-Order PWM DC-DC Converters

Hopf-Type Intermediate-Scale Bifurcation in Single-Stage Power-Factor-Correction Power Supplies

Incorporating Back Telemetry in a Full-Wave CMOS Rectifier for RFID and Biomedical Applications

Low-Power Low-Noise Neural Amplifier in 0.18μm FD-SOI Technology

Wireless Implant Communications for Biomedical Monitoring Sensor Network

A CMOS Contact Imager for Cell Detection in Bio-Sensing Applications

A Matching Technique for Biphasic Stimulation Pulse

A Simultaneous Div-Curl 2D Clifford Fourier Transform Filter for Enhancing Vortices, Sinks and Sources in Sampled 2D Vector Field Images

Direct Batch Evaluation of Desirable Eigenvectors of the DFT Matrix by Constrained Optimization

An Efficient Identification Algorithm for FIR Filtering with Noisy Data

A New Minimum Variance Spectral Estimation Method for Analyzing Click-Evoked Otoacoustic Emissions

A novel motion detection pointing device Using a binary CMOS image sensor

Spike Events Processing for Vision Systems

Fast sensory motor control based on event-based hybrid neuromorphic-procedural system

Address-Event Video Streaming over Wireless Sensor Networks

Quantifying Input and Output Spike Statistics of a Winner-Take-All Network in a Vision System

High-Speed Serial AER on FPGA

Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks

Power Reduction of On-Chip Serial Links

Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management

Reconfigurable Clock Distribution Circuitry

Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects

Global Interconnect Optimization in the Presence of On-chip Inductance

A Novel Design Methodology of the On-Chip Power Distribution Network Enhancing the Performance and Suppressing EMI of the SoC

Asymmetric clock driver for improved power and noise performances

Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders

Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture

Towards Gb/s turbo decoding of product code onto an FPGA device

Low-latency Memory-efficient 150-Mbps Turbo FEC Encoder and Decoder

Efficient Message Passing Architecture for High Throughput LDPC Decoder

An Efficient Oscillator Design Based on OTA Nonlinearity

Application of Pulsed Digital Oscillators in `reverse mode' to eliminate undesired vibrations in high-Q MEMS resonators

CMOS Current-controlled Oscillators

A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-μm CMOS Process

A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs

Highly Linear V/I Converter with Programmable Current Mirrors

Electrical Stress-free High Gain and High Swing Analog Buffer Using an Adaptive Biasing Scheme

A SiGe BiCMOS Variable Gain Amplifier for Cryogenic Temperature Applications

Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits

A Fully Integrated Architecture for Fast Programming of Floating Gates

Incremetal Spatio-Temporal Feature Extraction and Retrieval for Large Video Database

A Missing Data-based Feature Fusion Strategy for Noise-Robust Automatic Speech Recognition Using Noisy Sensors

Gait Analysis for Human Identification through Manifold Learning and HMM

Efficient Multi-Hypothesis Error Concealment Technique for H.264

Optimized multi-path routing using dual decomposition for wireless video streaming

Content-Adaptive Wavelet-Based Scalable Video Coding

An Object-based Approach to Plenoptic Video Processing

A Human Vision System based Flash Picture Coding Method for Video Coding

Disparity Estimation and Virtual View Synthesis from Stereo Video

Low-delay View Random Access for Multi-view Video Coding

System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint

Global Asymptotic Stability of Recurrent Neural Networks with Time Varying Delays

Upper-Triangulization of Non-Symmetric Matrices Using Sanger's Type Learning Systems

Accurate Modeling of Drain Current Derivatives of MESFET/HEMT Devices for Intermodulation Analysis

Cort-X II: low power element design of a large-scale spatio-temporal pattern clustering system

Automatic Detection of Solder Joint Defects on Integrated Circuits

Minimum-Cost Load Balancing Document Distribution in Distributed Web Server Systems

Topology design for fast convergence of network consensus algorithms

Cellular Automata with Large Channel Separations

Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units

2-MITE Product-of-Power-Law Networks

DTS: A Tree Based Representation for 3D-Block Packing

Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring

Thermal Modeling and Temperature Driven Placement for FPGAs

Two Clustering Preprocessing Techniques for Large-Scale Circuits

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew

Programmable Routing Tables for Degradable Torus-Based Networks on Chips

A Study on Impact of Leakage Current on Dynamic Power

Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency

Effective Acceleration of Iterative Slack Distribution Process

Design and Synthesis of a Three Input Flagged Prefix Adder

Designing Efficient Online Testable Reversible Adders With New Reversible Gate

Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder

High Speed 1-bit Bypass Adder Design for Low Precision Additions

A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems

Implementation of a Labeling Algorithm based on Contour Tracing with Feature Extraction

Flexible and Cost Effective Transport Stream Processor for DTV

Efficient Color Space Conversion using Custom Instruction in a RISC Processor

A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance

Flexible Low Power Probability Density Estimation Unit For Speech Recognition

Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees

Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN)

Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis

A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation

Clock Gating and Negative Edge Triggering for Energy Recovery Clock

Efficient Power Macromodeling Technique for IP-Based Digital System

A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control

Impact of strain on the design of low-power high-speed circuits

An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop

Optimal Body Biasing for Minimum Leakage Power in Standby Mode

A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio

A Low Energy FFT/IFFT Processor for Hearing Aids

Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency

High performance processor array for image processing

The RunBot Architecture for Adaptive, Fast, Dynamic Walking

ISCAS Special Session Demo: Wireless Video Sensor for Ad-hoc Networks

Silicon Neurons that Inhibit to Synchronize

A Self-Contained Large-Scale FPAA Development Platform

Using FPGA for visuo-motor control with a silicon retina and a humanoid robot

Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensor

Battery powered high dynamic range vision system

AER Auditory Filtering and CPG for Robot Control

An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell Recordings

A Universal Method for Hierarchical Object Recognition based on Low-Power Vision Sensors

Thresholded samplers for UWB impulse radar

Data Matrix Code Recognition Using the Eye-RIS Vision System

An On-line, Multi-Parametric, Multi-Channel Physicochemical Monitoring Platform for Stem Cell Culture Bioprocessing

A Micropower Cochlear Prosthesis System Demonstrator

A Prototyping Co-design Platform with A Simplified Architecture for Video Codec Implementation

Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACs

A Continuous Time Analog-to-Digital Converter With 90μW and 1.8μV/LSB Based on Differential Ring Oscillator Structures

Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCs

"Split-ADC" Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADC

A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs

Device Mismatch: An Analog Design Perspective

Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits

Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS

An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron Technologies

Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates

Effect of Recompression on Attacking JPEG Steganographic Schemes An Experimental Study

Data Hiding For Binary Images Authentication By Considering A Larger Neighborhood

Enhanced Image Trans-coding Using Reversible Data Hiding

Cost Effective Color Filter Array Demosaicking with Chrominance Variance Weighted Interpolation

Color Demosaicking Using Direction Similarity in Color Difference Spaces

A Simple Neural Cross-Correlation Engine

An Energy-Scalable Margin Propagation-Based Analog VLSI Support Vector Machine

Neural Learning by Retractions on Manifolds

A Scalable and Programmable Architecture for the Continuous Restricted Boltzmann Machine in VLSI

A Current-Mode Analog Circuit for Reinforcement Learning Problems

Reduced Complexity Space-Time-Frequency Model for Multi-Channel EEG and Its Applications

On the Time-frequency Analysis of Trunk Muscles During Sudden Release of Load

3D Shape Acquisition System Dedicated to a Visual Intracortical Stimulator

d-infinite Criteria for MEG Characterization

Design and Implementation of a Low Complexity Near-lossless Image Compression Method for Wireless Endoscopy Capsule System

Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding

On equalization of channels with ZP precoders

An Adaptive Step-size Order Statistic Time Domain Equaliser for Discrete Multitone Systems

Training-Based Estimation of Correlated MIMO Fading Channels in the Presence of Colored Interference

An Efficient Finite Precision Realization of the Adaptive Decision Feedback Equalizer

Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks

A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous Applications

An Inductor-less Micro Solar Power Management System Design for Energy Harvesting Applications

Design and Implementation of Routing Scheme for Wireless Network-on-Chip

Data Throughput Optimization in the IEEE 802.15.4 Medical Sensor Networks

Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder

Hardware Architecture of a Parallel Pattern Matching Engine

A Hardware Efficient Very Large Bit Word Binary to Double Base Number System Converter for Encryption Applications

An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform

An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation

Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers

Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions

Power Grid Analysis of Dynamic Power Cutoff Technology

Multi-Vth Level Conversion Circuits for Multi-VDD Systems

A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme

A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints

Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes

Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding

FFT Processor for OFDM Channel Estimation

VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition

Algorithmic ADC Offset Compensation by Non-White Data Chopping

Stability Analysis of RED Gateway with Multiple TCP Reno Connections

Noncoherent Correlation-Based Communication Systems Choosing Different Chaotic Maps

Second-level NIST Randomness Tests for Improving Test Reliability

Joint Design of a DS-UWB Modulator and Chaos-Based Spreading Sequences for Sensor Networks

CMOS Integrated LC RF Bandpass Filter with Transformer-Coupled Q-Enhancement and Optimized Linearity

Techniques for Dual-Band LNA Design using Cascode Switching and Inductor Magnetic Coupling

A New CMOS 3.1-11.7 GHz Low Power LNA for Ultra-Wideband Wireless Applications

A CMOS Variable Gain Front-end for a WCDMA Receiver

Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation Oscillator

Parallel current-steering D/A Converters for Flexibility and Smartness

A 12-bit Current-Steering DAC with Calibration by Combination Selection

Power/Area Trade-Offs in Low-Power/Low-Area Unary-R-2R CMOS Digital-to-Analog Converters

A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's

Multi-level Order Reduction with Nonlinear Port Constraints

Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation

Analysis for Signal and Power Integrity Using the Multilayered Finite Difference Method

Macromodeling for Nonlinear Distributed Interconnect Networks

Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering Techniques

An Efficient Joint Source-Channel Coding for Wavelet Based Scalable Video

Error-Resilience Transcoding of H.264/AVC Compressed Videos

UEP for Progressive Image Transmission with GA-based Optimization

Iterative Joint Source-Channel Decoding of H.264 Compressed Video

XML-driven Exploitation of Combined Scalability in Scalable H.264/AVC Bitstreams

Configuring of Spiking Central Pattern Generator Networks for Bipedal Walking Using Genetic Algorthms

Spike-Based Feature Extraction for Noise Robust Speech Recognition Using Phase Synchrony Coding

Self-Organizing Map Considering False Neighboring Neuron

LVDS Serial AER Link performance

Synchronization and Bifurcations in Networks of Coupled Hindmarsh-Rose Neurons

Electromagnetic Compatibility Modeling in Low-Noise Medical Sensor Interfaces

Impact of Control Signal Non-Idealties on Two-Phase Charge Pumps

Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop

Above Threshold pFET InjectionModeling intended for ProgrammingFloating-Gate Systems

A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD

An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable Multiprocessor

A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and Reverberation

Address Code Optimization Exploiting Code Scheduling in DSP Applications

A Precompensation Algorithm for PWM-Based Digital Audio Amplifiers for Portable Applications

Denoising for Generalized Sidelobe Canceller

Design and Implementation of a Low-power Baseband-system for RFID Tag

Enabling Pervasive Sensing with RFID: An Ultra Low-Power Digital Core for UHF Transponders

A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications

Object Tracking Based on RFID Coverage Visual Compensation in Wireless Sensor Network

Low-Complexity Encryption Using Redundant Bits and Adaptive Frequency Rates in RFID

An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing

Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator

A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder

MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV

A New Frame Recompression Algorithm Integrated with H.264 Video Compression

A Low Power Domino with Differential-Controlled-Keeper

Towards Automated Power Gating of Registers using CoDeL

Self-Supplied Integrable Active High-Efficiency AC-DC Converter for Piezoelectric Energy Scavenging Systems

Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control

A New Statistical Approach for Glitch Estimation in Combinational Circuits

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

A High Throughput H-QC LDPC Decoder

FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding Algorithm

Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes

Design and Realization of Analog Phi-Function for LDPC Decoder

Classes of stochastically switched (blinking) systems

Synchronization in Complex Hybrid Networks

Dynamics of a Logarithmic Transimpedance Amplifier

Equivalence of two discretization schemes in a simple sliding mode control system

Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic Signals

A Design of DC Offset Canceller using Parallel Compensation

A Second Order ΔΣ Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer

A Power Optimized Base-Band Circuitry for the Low-IF Receivers

A 90nm Quadrature Generator with Frequency Extension up to 4GHz

A New Quadrature LC-Oscillator

Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter

A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 μm CMOS

A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface

An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage

A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch

Satellite Navigation: New Signals, New Challenges

Analysis and Compensation of RF Impairments for Next Generation Multimode GNSS Receivers

Efficient Software Defined Radio Implementations of GNSS Receivers

Galileo L1 Civil Receiver Tracking Loops' Architecture

Design of an Assisted GPS Receiver and its Performance Analysis

Rate Control for Spatial/CGS Scalable Extension of H.264/AVC

Multi-Stage MCTF Coding Efficiency Analysis with Directed-Tree Model

3D Object-based Scalable Wavelet Video Coding with Boundary Effect Suppression

Balanced Inter-Layer Prediction for Combined Coarse Granular Scalability and Spatial Scalability

Macroblock-Based Adaptive In-Scale Prediction for Scalable Video Coding

A Study of Delay-Dependent Stabilization for Discrete-Time Systems with Time Delays

Noise-robust automatic speech recognition using a discriminative echo state network

Multi-Channel Coherent Detection for Delay-Insensitive Model-Free Adaptive Control

Generalizations of Oja's Learning Rule to Non-Symmetric Matrices

Effective Search with Hopping Chaos for Hopfield Neural Networks Solving QAP

A Structured ASIC Design Approach Using Pass Transistor Logic

Architecture Level Power-Performance Tradeoffs for Pipelined Designs

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework

Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications

Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design

DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure

An Accurate Algorithm for Fast Frequency Warping

Minimum Variance Spectral Estimation-Based Time Frequency Analysis for Nonstationary Time-Series

Improved SVD-Based Technique for Enhancing the Time-Frequency Representation of Signals

HRTF Interpolation Through Direct Angular Parameterization

New Architectures for Low-Cost Public Key Cryptography on RFID Tags

Public-Key Cryptography on the Top of a Needle

ECC Processor with Low Die Size for RFID Applications

Strong Crypto for RFID Tags - A Comparison of Low-Power Hardware Implementations

New Light-Weight Crypto Algorithms for RFID

SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier

A New Compact Architecture for AES with Optimized ShiftRows Operation

Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes

A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128

High-Speed Parallel Hardware Architecture for Galois Counter Mode

Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM

Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM

Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor Platforms

A Microwave OTA Using a Feedforward-Regulated Cascode Topology

GVD and PMD Compensation Using a Linear Adjustable Filter Prototype in a 40 Gb/s OSSB System

A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures

On the Persistency of Excitation for Blind Channel Estimation in Cyclic Prefix Systems

Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems

Low Voltage CMOS Current and Voltage References without Resistors

A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design

A Capacitor-Free CMOS Low-Dropout Regulator

A gm-C Ramp Generator for Voltage Feedforward Control of DC-DC Switching Regulators

An Improved Temperature Compensation Technique for Current Biasing

A numerical design approach for single amplifier, Active-RC Butterworth filter of order 5

Volterra Analysis Using Chebyshev Series

Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCs

Design Centering High Frequency Integrated Continuous-Time Filters

On the Linearization of MOSFET Capacitors

A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC

Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs

A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter

Theory and Implementation of an Analog-to-Information Converter using Random Demodulation

An 8-bit Switched-Resistor Pipeline ADC

SiGe 77GHz Automotive Radar Technology

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples

SiGe IC- based mm-wave imager

60 GHz SiGe-BiCMOS Radio for OFDM Transmission

CMOS Transceivers at 60 GHz and Beyond1

An Irregular Search Window Reuse Scheme for Motion Estimation in MPEG-2 to H.264 Transcoding

Motion Mapping for MPEG-2 to H.264/AVC Transcoding

Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV Applications

Complexity Reduction of H.263 to H.264 Transcoder with Fast Mode Decision

Quality Enhancement in H.264 Transform Domain Downsizing

Low-noise CMOS Fluorescence Sensor

Design, Analysis and Implementation of Integrated Micro-Thermal Control Systems

Biosensor Integrated with Transducer to Detect the Glucose

Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis

A multi-microchip retinal stimulator for in vitro / in vivo experiments

Noise-Aware Floorplanning for Fast Power Supply Network Design

Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout Design

A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building

A Fast 3D-BSG Algorithm for 3D Packing Problem

Design of FIR Filters with Discrete Coefficients via Polynomial Programming: Towards the Global Solution

Synthesis of Wideband Linear-Phase FIR Filters with a Piecewise-Polynomial-Sinusoidal Impulse Response

The Design of Symmetric Square-Root Pulse-Shaping Filters for Transmitters and Receivers

Analytical Design of an Equiripple DC-Notch FIR Filter

A Sequential Constrained Least-Square Method for Minimax Design of Linear-phase FIR filters with Time-domain Constraints

Low-Power Circuits for Brain-Machine Interfaces

Miniature Implantable System Dedicated to Bi-Channel Selective Neurostimulation

A Fully Integrated Fail-safe Stimulator Output Stage Dedicated to FES Stimulation

Designing Efficient Inductive Power Links for Implantable Devices

Florida Wireless Implantable Recording Electrodes (FWIRE) for Brain Machine Interfaces

CSI-aided Demapping of Dual-Carrier Modulation for Multiband-OFDM

Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H

Parallel Architecture of List Sphere Decoders

FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh

A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling

Profile-Based Low Power Scheduling for Conditional Task Graph: A Communication Aware Approach

Adaptive Clock Gating Technique for Low Power IP Core in SoC Design

Quasi-Static Energy Recovery Logic with Single Power-Clock Supply

A Two-port GFSK Direct Modulator for Wideband Applications at 5.8 GHz

Integrated Linear AC-coupling Circuit for DC-Balanced and Non-Balanced Traffics

A 3.7mW, 1.6V CMOS Analog Adaptive Equalizer for a 125Mbps Wire-Line Transceiver

Quadrature VCOs Based on Coupled PLLs

Modified Reduced Constellation PLL for Higher Order QAM

86 dB DR Cross-Coupled Time-Interleaved xx ADC for Audio Signal Band with 322 ΣA Current Consumption

Low-Voltage Low-Power CMOS Oscillator with Low Temperature and Process Sensitivity

A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma Modulation

A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme

A Sub-1V Low Power Temperature Compensated Current Reference

VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response Filter

Current-Mode Phase-Locked Loops with Low Supply Voltage Sensitivity

On-Chip Substrate Noise Suppression Using Clock Randomization Methodology

Noise Figure Measurement Using Mixed-Signal BIST

Congruence Synchronous Mirror Delay

Dual Active-Capacitive-Feedback Compensation for Area-Efficient Three-Stage Amplifiers

A 4-channel 12.5Gb/s Common-Gate Transimpedance Amplifier Array for DVI/HDMI Applications

High-Accuracy, High-Precision DEM-CCII Amplifiers

Low-Voltage CMOS Single Ended and Fully Differential Amplifier with Programmable Gain.

Mismatch-tolerant, Continuous Time, Gain Enhanced Amplifiers

The Impact of Different Gain Control Methods on Performance of CMOS Variable-Gain LNA

Rosenstark-like Representation of Feedback Amplifier Resistance

Miller Compensation: Optimization with Current Buffer/Amplifier

Low-Voltage Wilson Current Mirrors in CMOS

A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback

On Problems of Compensated Continuous-Time Chebyshev Filters in the Time Domain

Analysis of Continuous-Time Digital Signal Processors

A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C Filters

Source-degenerated CMOS Transconductor with Auxiliary Linearization

Simplified Low-Voltage CMOS Syllabic Companding Log Domain Filter

Analysis of Second-Order Modes of Linear Continuous-Time Systems under Positive-Real Transformations

Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCs

CMOS Inductor Performance Estimation using Z- and S-parameters

An Algorithm for Automatic Tuning of PLLs

Estimating Circuit Nonidealities of Continuous-Time Multibit Delta-Sigma Modulators

Increasing the Sense Margin of 1T-1C Ferroelectric Random-Access Memories

Fault Tolerance Circuit for AM-OLED

Chopper Modulation Improves OTA Information Transmission

Temperature-Robust Performance Yield through Supply Voltage Selection

Subwavelength Plasmonic Bragg Reflector Structures for On-chip Optoelectronic Applications

Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems

An Efficient Method for Estimation of Autoregressive Signals Subject to Colored Noise

Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power Amplifiers

PLL-Free Quadrature-Amplitude Modulation in Coherent Optical Communication

Peak-Contrained WLS Strategy for FIR Digital Filter Design

Eigenvector and Fractionalization of Discrete Hadamard Transform

Noise Reduction System Based on LPEF and System Identification with Variable Step Size

Lagrangian Gradient for Principal Singular Component Analysis

Discrete Stockwell Transform and Reduced Redundancy Versions from Frame Theory Viewpoint

Nonlinear Compensation for High Power Amplifiers using Genetic Programming

A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR Filters

A Diversity Controlled Genetic Algorithm for Optimization of FRM Digital Filters over DBNS Multiplier Coefficient Space

Complexity Comparison of Linear-Phase Mth-Band and General FIR Filters

IIR Digital Filter Design with Novel Stability Criterion Based on Argument Principle

FIR Filter Approximation by IIR Filters Based on Discrete-Time Vector Fitting

New Spatially Adaptive Wavelet-based Method for the Despeckling of Medical Ultrasound Images

A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications

A Low Power Digital Baseband for Wireless Endoscope Capsule

A Wide Tuning Range CMOS Oscillator for an Optoelectronic Retinal Prosthesis System

Ultra Low-Power Sensor Node for Wireless Health Monitoring System

A Safe Transmission Strategy for Power and Data Recovery in Biomedical Implanted Devices

Area-Power Efficient Lifting-Based DWT Hardware for Implantable Neuroprosthetics

A Bio-Inspired Adaptive Retinal Processing Neuron with Multiplexed Spiking Outputs

A New Handheld Biochip-based Microsystem

An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier

A Basilar Membrane Resonator for an Active 2-D Cochlea

Circuit Techniques for Reducing Low Frequency Noise in Optical MEMS Position and Inertial Sensors

A CMOS Image Sensor with Focal Plane Discrete Cosine Transform Computation

A CMOS Image Sensor using Variable Reference Time Domain Encoding

New Recursive Adaptive Beamforming Algorithms for Uniform Concentric Spherical Arrays with Frequency Invariant Characteristics

Complex Phenomena in SEPIC Converter Based on Sliding Mode Control

A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile Memories

CMOS Integrated Highly Efficient Full Wave Rectifier

Boundaries Between Fast-and Slow-Scale Bifurcations in Parallel-Connected Buck Converters

General-purpose ripple-based fast-scale instability prediction in switching power regulators

Analysis of an Adaptive Filter-bank for Harmonic Measurement and Estimation

Short Circuit Current of Induction Generators

A Low-power Sensorless Inverter Controller of Brushless DC Motors

Incremental Power Impedance Optimization Using Vector Fitting Modeling

Risk Management - beyond Risk Analysis

A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop

A 5 Meps $100 USB2.0 Address-Event Monitor-Sequencer Interface

A Silicon-on-Sapphire Low-Voltage Temperature Sensor for Energy Scavengers

On a novel Hybrid LQ-MCS control strategy and its application to a DC motor

A Converter with Fixed Switching Frequency Adaptive Multi-Mode Control Scheme

A General Noncoherent Chaos-Shift-Keying Communication System and its Performance Analysis

A Method to Reduce the Effect of the Switching Noise in Analog-Mixed Circuits

Occasional Delayed Feedback Control for Switched Autonomous Systems

Performance of Multi-User DCSK Communication System Over Multipath Fading Channels

A Chaos-Modulated Dual Oscillator-Based Truly Random Number Generator

Phase Synchronization in Injection-'Un'locking Oscillator Arrays

Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology

Adaptive Pinning Synchronization of A General Complex Dynamical Network

Vertically-Integrated Three-Dimensional SOI Photodetectors

Distributed Optimization Over Wireless Sensor Networks using Swarm Intelligence

Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition

A New 10 Gbps Traffic Management algorithm for High-speed Networks

An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio Receivers

Frequency Response Masking based Reconfigurable Channel Filters for Software Radio Receivers

On the Suitability of Discrete-Time Receivers for Software-Defined Radio

Improved Factorization for Sample Rate Conversion In Software Defined Radios

A Parallel, Multi-Resolution Sensing Technique for Multiple Antenna Cognitive Radios

A CMOS Direct-Digital BPSK Modulator Using an Active Balun and Common-Gate Switches

A 2.5 Gb/s CMOS Burst-Mode Limiting Amplifier for GPON System

50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm Process

A 3.8-Gb/s CMOS Laser Driver with Automatic Power Control Using Thermistors

A New CMOS BPSK Modulator with Optimal Transaction Bandwidth Control

All-CMOS High-Speed CML Gates with Active Shunt-Peaking

The Wide Input Range Automatic-Threshold Control Circuit for High Definition Digital Audio Interface

Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance

A Fully Integrated 2.4GHz CMOS Frequency Synthesizer Using a Ring-Based VCO with Inductive Peaking

Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal Processors

Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System

An Energy-Proportion Synchronization Method for IR-UWB Communications

Multiuser Detection Based on Particle Swarm Optimation Algorithm

Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems

Modified SDF Architecture for Mixed DIF/DIT FFT

Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System

Effect of Word-length Precision on the Performance of MIMO Systems

A Novel Low-Complexity Rayleigh Fader for Real-Time Channel Modeling

A Real-Time Digital Baseband MIMO Channel Emulation System

Efficient Complex Matrix Inversion for MIMO Software Defined Radio

CMOS Millimeter-Wave Signal Sources and Detectors

A 1.5-V Low-Power Common-Gate Low Noise Amplifier for Ultrawideband Receivers

Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks

A Subharmonic Injection-Locked Self-Oscillating Mixer

Mixing in a 220MHz CMOS-MEMS

A Brief Overview of the Complex Biological and Engineering Networks

On two approaches to analyzing consensus in complex networks

Enhancing Synchronizabilities of Power-Law Networks

Identification and monitoring of biological neural network

Synchronization of the Time-Varying Discrete Biological Networks

Image Quality Assessment using Foveated Wavelet Error Sensitivity and Isotropic Contrast

Pixel-Level Image Fusion Scheme based on Linear Algebra

Motion Adaptive Deinterlacing via Edge Pattern Recognition

Background stabilization and debris flagging in launch pad videos

Low-Complexity and Reliable Moving Objects Detection and Tracking for Aerial Video Surveillance with Small UAVS

CNN Implementation of Spin Filters for Electronic Speckle Pattern Interferometry Applications

Evolution of Pixel Level Snakes towards an efficient hardware implementation

Area and Time Efficient Cellular Non-linear Networks

An Organic Computing architecture for visual microprocessors based on Marching Pixels

A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual Stimulus

On the Effectiveness of Reducing Large Linear Networks with Many Ports

Noise Simulation and Modeling for MEMS Varactor Based RF VCOs

GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis

Fast Transient Simulation of Lossy Transmission Lines

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect

Design of IIR Variable Fractional Delay Digital Filters

On Frequency-Weighted l2-Sensitivity Analysis and Minimization of 2-D State-Space Digital Filters Subject to l2-Scaling Constraints

A Fast Convergence Algorithm for L2-Sensitivity Minimization of 2-D Separable-Denominator State-Space Digital Filters

Digital Integrator Design Using Recursive Romberg Integration Rule and Fractional Sample Delay

A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip

Dynamic Reconfigurability in Embedded System Design

System-Level Design for Partially Reconfigurable Hardware

Dynamically Swappable Hardware Design in Partially Reconfigurable Systems

Modeling and Synthesis of Hardware-Software Morphing

Automated HDL Generation: Comparative Evaluation

A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications

Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes

Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part II - FPGA Implementation

A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method

Evaluation of High Throughput Turbo-Decoder Architectures

High Read Stability and Low Leakage Cache Memory Cell

Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology

Nonvolatile Flash Memories in Silicon-on-sapphire CMOS

Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories

An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM

A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOS

An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock Jitter

A Multi-band CMOS Low Noise Amplifier for Multi-standard Wireless Receivers

A Fully Integrated Inductorless Low Noise Amplifier with 1dB-Step Programmable Gain for FM Radio Receiver Front-End

Exploration of energy requirements at the output of an LNA from a thermodynamic perspective

State-Space Analysis of Power Complementary Analog Filters

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

Optimal Synthesis of MITE Translinear Loops

Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors

Linear Current Division Principles

Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) Approach

A CMOS Front-End for a Lossy Image Compression Sensor

Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout Transistors

Two Transistor Current Mode Active Pixel Sensor

A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

On the Design of Error Cancellation Network for MASH ΣΔ-Frequency discriminators

Design of Very Low Noise 4.2GHz Clapp VCOs

A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output Power

Precise RSSI with High Process Variation Tolerance

Enabling Technologies in Drug Delivery and Clinical Care

Study of CuO Nanoparticle-induced Cell Death by High Content Cellular Fluorescence Imaging and Analysis

Gold-Based Nanoparticles for Breast Cancer Diagnosis and Treatment

Localized closed-loop temperature control and regulation in hybrid silicon/silicone life science microsystems

Reliability Analysis of Physiological Phenomena by Cardiac Action Potential Model

Architecture for Multiple Reference Frame Variable Block Size Motion Estimation

Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding

Video Segmentation with Model-Based Sprite Generation for Panning Surveillance Cameras

Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC Decoder

A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264

Models of Lava Flow Through the CNN-Based E^3 Architecture

Applying CNN to Cheminformatics

Modeling of self-adaptive systems with SCADE

Probabilistic Modelling of Phase-tuned Disparity Energy Neuron Populations

On the Implementation of Cellular Wave Computing Methods by Hardware Learning

A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits

Scalable Gate-Level Models for Power and Timing Analysis

Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio Receivers

FRM Filter Design with Group Delay Constraint Using Second-Order Cone Programming

Complexity Reduction of FRM Filters via Multiplication-Free Prefilter-Equalizer Structures

FRM-Based FIR Filters with Minimum Coefficient Sensitivities

Design of Diamond and Circular Filters by Semi-definite Programming

An Online Procedure for Linear-Phase 2-D FIR Filters of Smallest Size with Magnitude Error Constraint

Improved Wideband Blind Adaptive System Identification Using Decorrelation Filters for the Localization of Multiple Speakers

Performance Evaluation of Convolutive Blind Source Separation of Mixtures of Unequal-Level Speech Signals

On Modelling the Frequency Components of Speech with Norm-Invariant Joint Densities

Robust blind dereverberation of speech signals based on characteristics of short-time speech segments

Joint Source-Channel Modeling and Estimation for Speech Dereverberation

Multiple-Width Bus Partitioning Approach to Datapath Synthesis

High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology

On the Hardware Reduction of z-Datapath of Vectoring CORDIC

Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

Circuit implementation of floating point range reduction for trigonometric functions

A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations

A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation

High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths

A Self-Biased Charge-Transfer Sense Amplifier

A 12-mW Fully Integrated Low-IF dual-band GPS Receiver on 0.13-μm CMOS

A CMOS Integrated Power Detector for UWB

4.7pJ/pulse 7th Derivative Gaussian Pulse Generator for Impulse Radio UWB

A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology

A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider

A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating over Seven Decades of Current

Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes

An Unconstrained Architecture for High-Order ΣΔ Force-Feedback Inertial Sensors

A Micropower Voltage, Current, and Temperature Reference for a Low-Power Capacitive Sensor Interface

High Precision 16-bit Readout Gas Sensor Interface in 0.13μm CMOS

An AER Contrast Retina with On-Chip Calibration

Motion Detection Circuits for a Time-To-Travel Algorithm

A Spike-Based Saccadic Recognition System

A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection Applications

Dichromatic spectral measurement circuit in vanilla CMOS

A Nonlinear Model for Phase Noise and Jitter in LC Oscillators

A Low Power BFSK Super-Regenerative Transceiver

A 0.18μm CMOS 2.1GHz Sub-sampling Receiver Front End with Fully Integrated Second- and Fourth-Order Q-Enhanced Filters

Diophantine Frequency Synthesis The Mathematical Principles

A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range

In Vitro Epileptic Seizure Prediction Microsystem

Implantable MEMS Accelerometer Microphone for Cochlear Prosthesis

Spike discrimination using amplitude measurements with a low-power CMOS neural amplifier

Using Pulse Width Modulation for Wireless Transmission of Neural Signals in a Multichannel Neural Recording System

A Wireless IC for Wide-Range Neurochemical Monitoring Using Amperometry and Fast-Scan Cyclic Voltammetry

Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders

A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique

Statistical Analysis Based H.264 High Profile Deblocking Speedup

Context-based Arithmetic Coding Reexamined for DCT Video Compression

An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVS

A Study on Convergence of Competitive CNNs

Sufficient Conditions for 1-D CNNs with Opposite-Sign Templates to Perform Connected Component Detection

Limit Cycles and Bifurcations in Nonlinear Oscillatory Networks

Small Amplitude, Phase Locked Response in Oscillatory Networks with Delays

Active Visual Tracking of Heading Direction By Combining Motion Energy Neurons

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

A Low-Cost Phase-Noise Cancellation Method for OFDM Systems

Fractionally Spaced Orthogonal Frequency Division Multiplexing Systems

Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part I - Algorithm

Breakdown Point Analysis of a New M-Estimator for Robust Multiuser Detection in Non-Gaussian Channels

A Multiplier Structure Based on a Novel Real-time CSD Recoding

High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing Applications

Scaled Lifting Scheme and Generalized Reversible Integer Transform

Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms

Low-power adaptive filter based on RNS components

Variability in VLSI Circuits: Sources and Design Considerations

Variability-Aware Synthesis for Wideband Low Noise Amplifiers

Attaining Thermal Integrity in Nanometer Chips

Substrate Noise Reduction Based On Noise Aware Cell Design

Leakage-Aware Design of Nanometer SoC

ECG Cancellation for Surface Electromyography Measurement Using Independent Component Analysis

Linear Prediction Based Semi-Blind Channel Estimation for MIMO-OFDM System

Noisy Component Extraction (Noice)

Measuring Dependence of Bin-wise Separated Signals for Permutation Alignment in Frequency-domain BSS

Closed Form Parameters Estimation for Near Field Sources

Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects

Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders

Digital Multiplication using Continuous Valued Digits

An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB Templates

Novel High-Speed Redundant Binary to Binary converter using Prefix Networks

A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters

A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters

CMOS High Power SPDT Switch using Multigate Structure

A Low Phase Noise Quad-Band CMOS VCO with Minimized Gain Variation for GSM/GPRS/EDGE

Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation

An Adaptive Quality-Factor Bandpass Filter

A Compact On-Chip Capacitive-Coupling Scheme for Very-Low Frequency Applications

A Practical CMOS Companding Sinh Lossy Integrator

A 0.18μm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels

Design of Systems with Prescribed Impulse Response Based on Second-Order Cone Programming

Single-Wafer Pressure Capacitive Sensor

CMOS Cantilever-based Oscillator for Attogram Mass Sensing

Simultaneous Measurement of Temperature and Lateral Force Using an Arc-Shaped FBG Sensor Module

Leakage-based On-Chip Thermal Sensor for CMOS Technology

A novel voltage-clamped CMOS ISFET sensor interface

Improvement of Bootstrapped Switch using Track and Precharge Phase

High-Voltage Analog Circuit Design using Thin-Oxide MOS Devices only

High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique

A Circuit-Based Noise Parameter Extraction Technique for MOSFETs

Monolithic Spiral Transformers: A Design Methodology

Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks

Transistor Channel Dendrites implementing HMM classifiers

Silicon neurons that burst when primed

Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons

Spike-based learning in VLSI networks of integrate-and-fire neurons

On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCs

A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS

Improved Background Algorithms for Pipeline ADC Full Calibration

A distortion model for pipeline Analog-to-Digital converters

A Pipelined A/D Conversion Technique with Low INL and DNL

Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity

On the Complexity of Three-Dimensional Channel Routing (Extended Abstract)

Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair

Application of Fast DC Analysis to Partitioning Hypergraphs

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement

A Pipelined Architecture Design for Trilateral Noise Filtering

A PDP Sub-field Coding Algorithm for the Reduction of Errors due to Line Load Variation

An Adaptive Block Size Phase Correlation Motion Estimation Using Adaptive Early Search Termination Technique

A Fast and reliable switching median filter for highly corrupted images by impulse noise

An OWE-based Algorithm for Line Scratches Restoration in Old Movies

High-Speed and Low-Cost Structures for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay Filters

A Simplified Structure for FIR Filters with an Adjustable Fractional Delay

Design of Allpass Fractional Delay Filter and Fractional Hilbert Transformer Using Closed-Form of Cepstral Coefficients

Closed-Form Design of Variable Fractional Order Integrator Using Complex Cepstrum

A Greedy Common Subexpression Elimination Algorithm for Implementing FIR Filters

Using H.264/AVC-based Scalable Video Coding (SVC) for Real Time Streaming in Wireless IP Networks

Fast Mode Decision Algorithms for Adaptive GOP Structure in the Scalable Extension of H.264/AVC

Scalable Video Streaming over Mobile WiMAX

Sliding-Window Digital Fountain Codes for Streaming of Multimedia Contents

Joint Source-Channel-Authentication Resource Allocation for Multimedia overWireless Networks

On the Performance of Two Constant Modulus Algorithms in Equalization with non-CM Signals

Combined Linear Prediction and Subspace Based Blind Equalizers

A proposal of a new blind equalizer using output signals of decision device

Eigenvector Algorithms for Blind Deconvolution of MIMO-IIR Systems

A Matrix Pseudo-Inversion Lemma and Its Application to Block-Based Adaptive Blind Deconvolution for MIMO Systems

Cache Miss-Aware Dynamic Stack Allocation

Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture

A Double-Issue Java Processor Design for Embedded Applications

Latency-Tolerant Virtual Cluster Architecture for VLIW DSP

A Low-cost and High-performance SoC Design for OMA DRM2 Applications

Simple design equations of gain compression and distortion spectrum in broadband RF transceivers

Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency Discriminator

Technique for Peak to Average Power Ratio Reduction suited for M-carrier WCDMA Base Station Transmitters

Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink Channels

Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation

Design of Precise Gain GmC-leapfrog Filters

A Novel CMOS Envelope Detector Structure

A 600mV 3.6mW 68dB DR 4th Order Analog Base Band Filter for WLAN Receivers

Analysis of Common-Mode Induced Even-Order Distortion in a Pseudo-Differential gm-C Filter

Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization

A 4 × 4 Logarithmic Spike Timing Encoding Scheme for Olfactory Sensor Applications

Incremental Encoder Based Position and Velocity Measurements VLSI Chip with Serial Peripheral Interface

Amperometric Readout and Electrode Array Chip for Bioelectrochemical Sensors

Digital Wideband Excitation Technique for Impedance-Based Structural Health Monitoring Systems

Bounded state space particle filter for network sensors

Voltage Elevator using a MEMS Resonator

High-speed front end for LED-Photodiode based fluorescence lifetime measurement system

A 12.4 ENOB Incremental A/D Converter for High-Linearity Sensors Read-Out Applications

Glass Break Detector Analog Front-End Using Novel Classifier Circuit

An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters

A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process

On-Line Histogram Equalization for Flash ADC

Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCs

Low-power design technique for flash A/D converters based on reduction of the number of comparators

A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs

Quadrature Mismatch Shaping Techniques for Fully Differential Circuits

Blue-Noise Sigma-Delta Modulator: Improving Substrate Noise and Nonlinear Amplifier Gain Effects

A 20-Bit Sigma-Delta D/A for Audio Applications in 0.13um CMOS

Designing Complex ΔΣ Modulators with Signal-Transfer Functions having Good Stop-Band Attenuation

An Efficient Intra Mode Selection Algorithm For H.264 Based On Fast Edge Classification

Improving Video Coding at Scene Cuts using Attention based Adaptive Bit Allocation

Improved Frame Level MAD Prediction and Bit Allocation Scheme for H.264/AVC Rate Control

Adaptive Lagrange Multiplier Selection for Intra-Frame Video Coding

Fast H.264 Inter Mode Decision Based on Inter and Intra Block Conditions

A Content-adaptive Fast Multiple Reference Frames Motion Estimation in H.264

A Genetic Rhombus Pattern Search for Block Motion Estimation

Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation

Low power variable block size motion estimation using pixel truncation

Motion Detection by Using Entropy Image and Adaptive State-Labeling Technique

SAT-based ATPG for Path Delay Faults in Sequential Circuits

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs

Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling

Watermarking for IP Protection through Template Substitution at Logic Synthesis Level

Design and Implementation of FPGA-based Systolic Array for LZ Data Compression

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs

Collaborative Routing Architecture for FPGA

A Parallel Face Detection System Implemented on FPGA

A design framework for FPGA-based dynamically reconfigurable digital controllers

An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects

Power Consumption Analysis of Flip-flop Based Interconnect Pipelining

Asynchronous Adiabatic Logic

A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction

Capacitively-Biased Floating-Gate CMOS: a New Logic Family

Delay Variability Due to Supply Variations in Transmission-Gate Full Adders

A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay

New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode

Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance

Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs

Application-Specific Instruction Generation for SOC Processors

A Flexible Embedded SRAM IP Compiler

A New Approach for Design and Verification of Transaction Level Models

Low Power ASIP Architecture Optimization based on Target Application Profiling

A Hold Friendly Flip-Flop For Area Recovery

On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs

Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem

Approximate Frequency Response Models for RLC Power Grids

Mismatch Compensated Design Techniques under Packaging-Induced Die Stress

1-V Linear CMOS Transconductor with -65 dB THD in Nano-Scale CMOS Technology

Dual-Output Trans-Impedance Amplifier of Cost-effective CMOS Optical Receiver for Digital Audio Interfaces

New squaring circuit with reduced sensitivity to element mismatches using differentially driven translinear cells

A 109 nW, 44 ppm/°C CMOS Current Reference with Low Sensitivity to Process Variations

Dynamic Eccentric Error Compensation for Track Following Control of Optical Disk Driver

CMOS Gyrator-C Active Transformers

Run-Time Programming of Analog Circuits Using Floating-Gate Transistors

An Undersampling Digital Microphone

Fractional-Rate FM-to-Digital Δ-Σ Converters

Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor

A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit

Low-Voltage Temperature-Independent Current Reference with no External Components

A new CMOS voltage reference scheme based on Vth-difference principle

A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation

A Sub-1V Low-Power High-Speed Static Frequency Divider

Design of a 1-Volt and μ-power SARADC for Sensor Network Application

A Novel Low Power BPSK Demodulator

Deterministic DEM DAC Performance Analysis

Process and Temperature Calibration of PLLs with BiST Capabilities

Low frequency, current mode programmable KHN filters using large-valued active resistors

A Fully Programmable Analog Window Comparator

Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC

Analog Implementation of a Mean Field Detector for Multiple Antenna Systems

Fast Peak Detector with Improved Accuracy and Linearity for High-Frequency Waveform Processing

A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications

A Wideband CMOS Mixer with Feedforward Compensated Differential Transconductor

High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator

A CMOS class-E Power Amplifiers with Power Control

A Low-Area, 0.18μm CMOS, 10Gb/s Optical Receiver Analog Front End

Dual Band Antenna Equalizer Realized by Utilizing 0.18μm Si-Processing Technology for a Pifa-900

A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver

A Power Efficient HBT Pulse Generator for UWB Radars

Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise Amplifiers

A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm

A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech Signals

Optimization of Gabor Features for Text-Independent Speaker Identification

A NMR Optimized Bitrate Transcoder for MPEG-2/4 LC-AAC

A Pitch Estimation Algorithm Based on the Smooth Harmonic Average Peak-to-Valley Envelope

An Approach for Voiced/Unvoiced Decision of Colored Noise-Corrupted Speech

Color Image Enhancement Based on Single-Scale Retinex With a JND-Based Nonlinear Filter

Efficient Intra Prediction in H.264 Based on Intensity Gradient Approach

Adaptive Search Range Motion Estimation Algorithm for H.264/AVC

Extraction and Integration of Human Body Parts for 3-D Motion Analysis of Golf Swing from Single-Camera Video Sequences

A 3D Integrated Feature-Extracting Image Sensor

A modular VLIW Processor

Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures

Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC

A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet Transform

Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform

On the Angular Decomposition Technique for Computing the Discrete Fractional Fourier Transform

2-D Tridiagonal IIR Filters/Systems: State Space and Circuit Realizations

Optimal Synthesis of State-Estimate Feedback Controllers with Minimum l2-Sensitivity and No Overflow Oscillations

Image Denoising using Shiftable Directional Pyramid and Scale Mixtures of Complex Gaussians

Sampling at Minimum Sampling Rate for Signals in Shift Invariant Spaces

A Low Power $Sinc^{3}$ Filter for ΣΔ Modulators

Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering

An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay Measurement

A Novel Fast Algorithm for Speech and Audio Coding

2006 IEEE International Symposium on Circuits and Systems

2005 IEEE International Symposium on Circuits and Systems

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

On-Chip Substrate Noise Suppression Using Clock Randomization Methodology

Content Provider	IEEE Xplore Digital Library
Author	Yuxin Wang Ignjatovic, Z.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Rochester Univ., NY (Yuxin Wang; Ignjatovic, Z.)
Abstract	We present a method for substrate coupling noise suppression that employs a pseudo-random clock. A pseudo-random sequence is utilized to randomize the pulse train of the system periodic clock effectively decorrelating its discrete spectral tones. Therefore, the discrete portion (spectral spikes) of the power spectral density of the regular clock is dispersed and the continuous (wide-band) portion of the spectrum rises as a noise floor. This work shows that there is a 22dB attenuation of the harmonic power by utilizing the clock randomization method with respect to the standard clocking scheme where the periodic clock signal is deployed.
Starting Page	2176
Ending Page	2179
File Size	342973
Page Count	4
File Format	PDF
ISBN	1424409209
DOI	10.1109/ISCAS.2007.378605
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Circuit noise Noise reduction Noise generators Digital circuits Current supplies Switching circuits Noise level Power supplies Wideband
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in