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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Baozhen Yu Bushnell, M.L. |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ (Baozhen Yu; Bushnell, M.L.) |
| Abstract | Dynamic power cutoff technique (DPCT) (Baozhen Yu and Bushnell, 2006) is a novel active leakage power reduction technique. It works by partitioning the circuit into different groups based on the minimal switching window of each gate and turning on the power of each group only during a small timing window within each clock cycle, which results in significant active leakage power savings. But this high frequency on-off operation on the power connections may cause power grid integrity issues. In this paper, the authors analyze DPCT's effect on the power grid. Experimental results on ISCAS '85 circuits using 70 nm Berkeley predictive models (Cao et al., 2000) show that DPCT reduces the maximal voltage drop on the power grid by up to 49%. However, it also introduces some high frequency harmonic noise. Extra decoupling capacitors can be added to reduce this high frequency noise to the required level. |
| Starting Page | 1393 |
| Ending Page | 1396 |
| File Size | 571660 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424409209 |
| DOI | 10.1109/ISCAS.2007.378488 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Power grids Power system dynamics Frequency Circuit noise Switching circuits Turning Timing Clocks Predictive models Voltage |
| Content Type | Text |
| Resource Type | Article |
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