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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Song Guo Hoi Lee |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Electr. Eng., Dallas Univ., Richardson, TX (Song Guo; Hoi Lee) |
| Abstract | This paper presents a dual active-capacitive-feedback compensation (DACFC) scheme for a three-stage amplifier in large capacitive-load applications. The proposed DACFC is first reported scheme, which can generate two left-half-plane zeros to compensate for the negative phase shift due to the amplifier non-dominant complex poles. The value of compensation capacitors can thus be significantly reduced to widen the gain-bandwidth product and decrease the chip area while maintaining the stability of the amplifier. Implemented in a standard 0.35mum CMOS process, the proposed amplifier only requires the total compensation capacitance of 4.3pF to achieve the gain-bandwidth product of 5.2MHz and the phase margin of 61deg when driving a 500pF//25kOmega load. The amplifier dissipates 330muW power under a 2V input supply. |
| Starting Page | 2188 |
| Ending Page | 2191 |
| File Size | 339827 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424409209 |
| DOI | 10.1109/ISCAS.2007.378608 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitors Frequency Bandwidth Power amplifiers Poles and zeros Stability CMOS process Parasitic capacitance Operational amplifiers Power integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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