NDLI: A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, R. Popovici, E.M. O'Flynn, B. O'Sullivan, M.E.
Copyright Year	2007
Description	Author affiliation: Dept. of Microelectron. Eng., Cork Univ. Coll. (Agarwal, R.; Popovici, E.M.)
Abstract	Hermitian codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to find a way of performing the required computations in a fast and memory efficient way so as to satisfy resource and throughput constraints imposed by the systems. The paper presents some architecture for Hermitian decoders which enhance their applicability in communication systems. Formulae and architectures for gap detection and address generation unit for satisfying memory constraints have been presented, which amount to 50% savings in storage area and 10% savings in the number of clock cycles reported in literature. A semi-parallel architecture is proposed as a solution to the latency and resource requirements tradeoff, which improves the throughput about q times compared to the word-serial architecture at an expense of some q times more adders, multipliers and simple multiplexers, where the code is defined over $GF(q_{2}).$ For a t error correcting code, the resource load of the parallel architectures is about gamma(t/q + (q-3)/4)( t/q + (q-3)/4 + 1) times this architecture, where gamma is the resource requirement ratio of a multiplier and an inverter
Starting Page	1405
Ending Page	1408
File Size	405038
Page Count	4
File Format	PDF
ISBN	1424409209
DOI	10.1109/ISCAS.2007.378491
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel architectures Decoding Throughput Computer architecture Memory management Clocks Delay Multiplexing Error correction codes Inverters
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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