NDLI: An Itra-high Speed Real-time T Processor

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Volume 2 - 2005

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2005 6th International Conference on ASIC Proceedings (IEEE Cat. No.05TH8820C)

2005 6th International Conference on ASIC Proceedings

Table of contents

Conference committee

Welcome to ASICON 2005

Opportunity and challenge for IC development in mainland of China

Design Automation in the "Late-CMOS" Age

The Secret Analog Revolution

ASICs in a Global Economy; The Industrialization of the Semiconductor Industry

Tutorial Session Index

Tutorial 1 Thermal-Aware Design Techniques for Nanometer VLSI Chip

Tutorial 2 Challenge to ASIC Design for Future Wireless Communication

Power reduction in high-speed inter-chip data communications

Low power design for embedded systems: today and tomorrow

Recent results in low power research

Challenges in the design of CMOS transceivers for the IEEE 802.11 wireless LANs: past, present and future

CMOS RF receiver: from system architecture to circuit implementation

Techniques for CMOS single photon imaging and processing

Challenge and opportunity in analog and RF electronics

Design for manufacturability: challenges and opportunities

Lithography-aware physical design

Taming the DFM beast into an adorable pet - a comprehensive approach

Design for manufacturing with increasing variability

SOC logic development using configurable, application-specific processors

An ASIC design of a novel pipelined and parallel sorting accelerator for a multiprocessor-on-a-chip

Optimizing SoC platform architecture for multimedia applications

Implementation of adaptive blind equalizer with carrier recovery for QAM receiver chip

A low power VLSI implementation for JPEG2000 codec

Evaluation of thermal-aware design techniques for microprocessors

A ew Charge-Pump based Countermeasure against ifferential Power Analysis

On-chip decoupling capacitor budgeting by sequence of linear programming

A novel asynchronous multiple function multiply-accumulator

Design methodology of low power JPEG2000 codec exploiting dual voltage scaling

A hardware efficient VLSI architecture for FFT processor in OFDM systems

A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection

Floating-point unit processing denormalized numbers

Fast and efficiently binding of functional units for low power design

Fast algorithm for leakage power reduction by input vector control

Low power SRAM design using charge sharing technique

An optimization of VLSI architecture for DFE used in Ethernet

iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target Environment

SLCAO: an effective system level communication architectures optimization methodology for system-on- chips

A low complexity near-lossless image compression method and its ASIC design for wireless endoscopy system

SoC design environment with automated configurable bus generation for rapid prototyping

Design of low-power double-edge triggered flip-flop

Leading zero anticipation for latency improvement in floating-point fused multiply-add units

A 64/spl times/64-bit modified Booth multiplier utilizing multiplexer-select Booth encoder

An innovative design of the DDR/DDR2 SDRAM compatible controller

Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator

Low power set-associative cache with single-cycle partial tag comparison

Hardware-software partition of fixed-point hardware accelerator from statistical perspective

A high-speed low-power D flip-flop

Challenges in PowerPC440-FS soft core development: timing perspective

Duplicated register file design for embedded simultaneous multithreading microprocessor

Codes reallocation and prediction for power efficiency in I-cache memory

An efficient low complexity LDPC encoder based on LU factorization with pivoting

To improve the voice quality over IP using channel coding

Considering The ffect Of Standard Cell Placement In Mi ed-Size Placement

Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage Scaling

Design of a high-speed low-power CAM

An efficient algorithm for nonpreemptive periodic task scheduling under energy constraints

High speed sense amplifier circuit for low-voltage SONOS memory systems

Bus buffer modeling and optimization for a microprocessor

A low-power baseband-processor for UHF RFID tag

High speed radix-16 design of a scalable Montgomery multiplier

Implementation of low-voltage true-single-phase-clocking (TSPC) logic using bulk dynamic threshold MOS technique

A new HW/SW co-design methodology to generate a system level platform based on LISA

New methods of FPGA co-verification for system on chip (SoC)

VLSI architecture of EBCOT tier-2 encoder for JPEG2000

An Itra-high Speed Real-time T Processor

Flexible platform design of IEEE 802.15.3a MAC over UWB with optimized protocol accelerator

Low-power adiabatic sequential circuits using two-phase power-clock supply

A hardware architecture of MIMO-OFDM synchronizer

AR AR /SO T AR CO- SI O A AVA CO-PROC SSOR OR A 3 -BIT RISC S ST MA T IMP M TATIO O T AR AR PARTITIO

Performance exploration and optimization of SDRAM-controller architecture on SDRAM access

Low-power FIR filter based on standard cell

Processor design considerations for wireless sensor network

High-performance and low-voltage challenges for sub-45nm microprocessor circuits

A VLSI architecture for motion compensation interpolation in H.264/AVC

A design of 500MHz 10-read 6-write register file

A low-power complementary pass-transistor tree multiplier based on adiabatic 4-2 compressors

An efficient architecture for computing division over GF(/sup 2/m) in elliptic curve cryptography

Silent CMOS circuits aiming for system-on-chip

A robust and low complexity implementation of synchronization for DVB-T receiver

Area-efficient VLSI architecture of joint carrier recovery and blind equalization for QAM demodulator

A high-performance low-power 2D 8/spl times/8 IDCT processor with asynchronous pipeline

A Modified ecimation ilter esign for Oversampled Sigma elta A/ Converters

An efficient equalizer for DVB-T receivers

A new algorithm of digital matched filter with a segment processing method

An implemented VLSI architecture of inverse quantizer for AVS HDTV video decoder

CMOS digital integrated temperature sensor

Clarifying the chaotic phenomenon in an MESFET oscillator by Lur's system form

VLSI architectures of domain adaptive fuzzy logic system

A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000

Reconfigurable VLSI architecture for VBSME in MPEG-4 AVC/H.264

A novel synchronization scheme in HDTV system with adaptive detection and low implementation complexity

Power Comple ity Analysis of Adiabatic SRAM

Design of adiabatic multi-port register file

Microprocessor development using SFL for educational purposes

Theory of current transmission switches and its application to design of a novel current-mode CMOS ternary Schmitt trigger

Design and implementation of an EOS chip

Five-valued circuit quantitative theory and design of five-valued twisted-ring counter

A voltage level converter circuit design with low power consumption

A 2.4 GHz Fully Integrated Class-A Power Ampifier In 0.35μm SiGe BiCMOS Technology

High efficiency, inductorless step-down DC/DC converter

A novel minimum-voltage active-clamping PFC controller

Analysis and design of Makowski charge-pump cell

Design and application of the novel low-threshold comparator using hysteresis

A 2.4-GHz Fully CMOS Integrated Transmitter for 802.1lb Wireless LAN

Wideband two-integrator oscillator-mixer

On-chip DC-DC voltage down converter for low-power IC chip

Design of a switched-current high-speed truly random number generator

An automatic calibration technique for the OPAMP and its former stage output offset

A novel method to realize automatic gain adjust for infrared readout integrated circuit

A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization technique

A new structure of low-noise CMOS differential amplifier

A fully CMOS-integrated pH-ISFET interface circuit

Non-traditional architectures for AD- and DA- converters

A novel low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

A direct conversion WLAN receiver

A 10-bit 30-MS/s 50mW pipelined A/D converter

A fast locking charge-pump PLL with adaptive bandwidth

A new high-speed low-voltage charge pump for PLL applications

A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver

A self-powered sensor module using vibration-based energy generation for ubiquitous systems

A CMOS differential current-controlled second generation current conveyor

A 12-bit 250-MHz current-steering DAC

A 1.8V transmitter for 10/100 Mbps Ethernet physical layer

A method to effectively decrease the settling time of gain-boost OTA

A phase-locked loop for receivers of UHF wireless microphone

A ully CMOS Integrated R Transceiver for biquitous Sensor etworks in Sub- z ISM-band

Circuit design and verification for ultra low current sensing amplifier aimed at bio-sensor applications

A novel clock and data recovery scheme based on sigma-delta quantization

Design of ultra wideband MOS differential VCO

A current-mode CMOS bandgap reference for differential signal processing

On-chip boost DC-DC converter in color OLED driver & controller ICs for mobile application

An intuitive implementation of continuous-time Gm-C filter

CMOS 1.5V bandgap voltage reference

A New Structure for Capacitor-Mismatch-Insensitive Multiply-By-Two Amplification

A mixed-signal driver chip for 65K-color passive-matrix OLED

A 40dB, 100MHz CMOS IF variable gain amplifier for DVB-C receivers

The design of a start-up circuit for boost DC-DC converter with low supply voltage

A CMOS correlator for UWB front-end circuit

A 5-GHz CMOS quadrature modulator for direct conversion transmitters

A 14-/spl mu/A 3-ppm//spl deg/C CMOS bandgap voltage reference

A BIPO AR Current Mirror ith ow Voltage

A new impedance matching method of CMOS mixer with common-source input stage

LCoS chip with integrated 8-bit gamma compensated digital data driver

2005 $6^{th}International$ Conference On ASIC Proceedings

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

2nd International Conference on ASIC

An Itra-high Speed Real-time T Processor

Content Provider	IEEE Xplore Digital Library
Author	Shiqun hang Dunshan Yu Shimin Sheng
Copyright Year	2005
Description	Author affiliation: Institute of Microelectronics, Peking University, Beijing 100871, P. R. China. Email: zhangsq@ime.pku.edu.cn (Shiqun hang)
Abstract	To meet the real-time demand of ultra-high speed, long size FFT in some specific communication or signal processing systems, a real-time FFT processor is presented in this paper, which can fulfill real-time demand of 512 points complex FFT at 1GHz sample rate. And with our strategy, longer size FFT can be implemented only adding some stage and enlarge the control counter. By paralleling data processing, we solve the problems coming with high clock frequency, such as power consumption and design complexity.
Starting Page	227
Ending Page	230
File Size	637411
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611291
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing algorithms Discrete Fourier transforms Hardware Real time systems Pipelines Microelectronics Clocks Frequency Energy consumption Computational complexity
Content Type	Text
Resource Type	Article

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