NDLI: A 10-bit 30-MS/s 50mW pipelined A/D converter

Content Provider	IEEE Xplore Digital Library
Author	Chen Xi He Lenian Yan Xiaolang
Copyright Year	2005
Description	Author affiliation: Inst. of VLSI Design, Zhejiang Univ., Hangzhou (Chen Xi; He Lenian; Yan Xiaolang)
Abstract	A 10-bit 30-Msample/s pipelined analog-to-digital converter is designed and implemented in a 0.6mum CMOS technology. Sampling capacitors scaling technique is employed to reduce the power dissipation. The digital correction technique is used to relax the offset requirement of the comparators. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The simulation and experiment results reveal that the ADC designed with this method achieves the SNDR of 58dB or the ENOB of 9.34 at full speed of 30MHz when input frequency is 7MHz. Furthermore, the ADC consumes only 50mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators
Starting Page	378
Ending Page	382
File Size	1735271
Page Count	5
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Analog-digital conversion Sampling methods Capacitors Power dissipation Distortion Linearity Design methodology Frequency Power supplies
Content Type	Text
Resource Type	Article

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