NDLI: Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator

Content Provider	IEEE Xplore Digital Library
Author	Jae-Gon Lee Woong Hwangbo Seonpil Kim Chong-Min Kyung
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon (Jae-Gon Lee; Woong Hwangbo; Seonpil Kim; Chong-Min Kyung)
Abstract	This paper describes top-down implementation of Rijndael, a new advanced encryption standard (AES), cipher for both encryption and decryption. Pipelined architecture was used to maximize the performance. The design started in the untimed functional level description in C. It was refined to behavioral-level design and finally to RTL design with SystemC. To overcome simulation performance degradation with RTL description, we adopted FPGA-based simulation accelerator in the final stage. To reuse the original test vectors, we introduced proxy module for interconnecting simulation environment with acceleration environment. This hides the presence of simulation accelerator from simulator and makes it possible to reuse test vectors of RTL simulation when simulation accelerator is present
Starting Page	68
Ending Page	72
File Size	2030166
Page Count	5
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611270
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Cryptography Testing Life estimation NIST Standards development Image generation Hardware Throughput Electronic mail
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in