NDLI: New methods of FPGA co-verification for system on chip (SoC)

Content Provider	IEEE Xplore Digital Library
Author	Lin Yi-fan Zeng Xiao-yang Wu Min Chen Jun Bao Rencheng
Copyright Year	2005
Description	Author affiliation: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai (Lin Yi-fan; Zeng Xiao-yang; Wu Min; Chen Jun; Bao Rencheng)
Abstract	With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI design, and it requires much more portion of time within the life circle of chip development. The time spent on the FPGA verification should be reduced to achieve a more efficient time-to-market for the IC product. Therefore, several strategies using both dynamic and static methods to execute this verification are proposed in this paper. By using a variety of techniques such as software static breakpoint monitoring and interrupt vectors remapping, the software verification is accelerated. A bus analyzer is adopted to provide real-time bus monitoring with a vivid evaluation of the system performance. In this paper, experiments show that above methods have greatly enhanced the efficiency and speed of the FPGA co-verification process
Starting Page	169
Ending Page	172
File Size	1162883
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611289
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays System-on-a-chip Monitoring Very large scale integration Chip scale packaging Time to market Acceleration Performance analysis Real time systems System performance Bus Monitoring SoC Co-Verification Interrupt Vectors Remapping Software Monitoring
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Field modifiable architecture with FPGAs and its design/verification/debugging methodologies

A VMM/FPGA co-verification method for “Longtium Stream” processor

A fast hardware/software co-verification method using a real hardware acceleration

FPGA verification methodology for SiSoC based SoC design

Field modifiable architecture with FPGAs and its design methodology

SoC systems thermal monitoring using embedded sensor cells unit

An automatic test approach for field programmable gate array (FPGA)

Design and verification of WISHBONE bus interface for System-on-Chip integration

Bus-Based and NoC Infrastructure Performance Emulation and Comparison

New methods of FPGA co-verification for system on chip (SoC)

Similar Documents

Field modifiable architecture with FPGAs and its design/verification/debugging methodologies

A VMM/FPGA co-verification method for “Longtium Stream” processor

A fast hardware/software co-verification method using a real hardware acceleration

FPGA verification methodology for SiSoC based SoC design

Field modifiable architecture with FPGAs and its design methodology

SoC systems thermal monitoring using embedded sensor cells unit

An automatic test approach for field programmable gate array (FPGA)

Design and verification of WISHBONE bus interface for System-on-Chip integration

Bus-Based and NoC Infrastructure Performance Emulation and Comparison

New methods of FPGA co-verification for system on chip (SoC)