NDLI: On-chip decoupling capacitor budgeting by sequence of linear programming

Content Provider	IEEE Xplore Digital Library
Author	Zhenyu Qi Hang Li Tan, S.X.-D. Yici Cai Xianlong Hong
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Riverside, CA (Zhenyu Qi; Hang Li; Tan, S.X.-D.; Yici Cai; Xianlong Hong)
Abstract	Excessive power supply noise increases propagation delay of switching gates and reduces noise margin of the circuit. Adding on-chip decoupling capacitors (decaps) is an effective way to reduce voltage noise in a on-chip power delivery system. In this paper, we propose an efficient and novel algorithm to allocate decaps in an area efficient way. The new algorithm applies the sequence of linear programming based approach to searching the minimum decap area to reduce voltage drop below user specified threshold. We show existing sensitivity based decap allocation algorithms tend to over estimate the decap areas due to nonlinear sensitivity dependence on decap values. Experimental results show that the proposed algorithm uses significantly less decap area than the existing conjugate gradient based approach but with similar CPU runtimes
Starting Page	98
Ending Page	101
File Size	1053685
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611252
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Linear programming Noise reduction Circuit noise System-on-a-chip Power supplies Propagation delay Switching circuits Threshold voltage Runtime
Content Type	Text
Resource Type	Article

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