NDLI: SLCAO: an effective system level communication architectures optimization methodology for system-on- chips

Content Provider	IEEE Xplore Digital Library
Author	Yawen Niu Jinian Bian Haili Wang Kun Tong Liang Zhu
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing (Yawen Niu; Jinian Bian; Haili Wang; Kun Tong; Liang Zhu)
Abstract	This paper proposes an effective system level communication architectures optimization (SLCAO) methodology to optimize the on-chip communication architectures (OCAs). SLCAO methodology divides the OCAs architecting into two steps: OCAs generation and OCAs optimization, and presents some valid bus mergence strategies to enhance the system performance and decrease the system cost from hierarchical buses through the analysis of the bus load. The methodology takes into account two categories of delay models, system delay model and PE-PE delay model, to evaluate the system performance and control the optimization process. The effectiveness of SLCAO methodology is illustrated by the 10-PEs example
Starting Page	33
Ending Page	36
File Size	2181221
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611263
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optimization methods System-on-a-chip Computer architecture System performance Hardware Character generation Cost function Performance analysis Delay systems Control system synthesis OCA communication synthesis optimization bus mergence hierarchical buses
Content Type	Text
Resource Type	Article

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