NDLI: A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver

Content Provider	IEEE Xplore Digital Library
Author	Lu Ping Wang Yan Li Lian Ren Junyan
Copyright Year	2005
Description	Author affiliation: State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China (Lu Ping; Wang Yan; Li Lian; Ren Junyan)
Abstract	A frequency synthesizer applied to 10/100 Base-T Ethernet transceiver is described. It can work in 10Mbps or 100Mbps mode adaptively and convert from one mode to another freely. The circuit can meet both requirements of transmitter on rising/falling time and receiver on CDR so that the additional power and area are saved. Under some testing circumstance, G of voltage control oscillator jitter/sub cycle-cycle/ is only 22ps with G of reference clock jitter/sub cycle-cycle/ 25ps (Herzel and Razavi, 1997). The testing result proves that the frequency synthesizer has good processing stability and rejection to noises. It works well for transmitter and receiver. The circuit is designed with SMIC 0.35/spl mu/m standard CMOS technology and the power supply is 3.3V.
Starting Page	391
Ending Page	394
File Size	1938757
Page Count	4
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611345
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency synthesizers Ethernet networks Transceivers Transmitters Circuit testing Jitter CMOS technology Voltage control Voltage-controlled oscillators Clocks 1280 Ethernet frequency synthesizer clock jitter EEACC: 1205 1230
Content Type	Text
Resource Type	Article

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