NDLI: Fast algorithm for leakage power reduction by input vector control

Content Provider	IEEE Xplore Digital Library
Author	Xiaotao Chang Dongrui Fan Yinhe Han Zhimin Zhang Xiaowei Li
Copyright Year	2005
Description	Author affiliation: Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China (Xiaotao Chang; Dongrui Fan; Yinhe Han; Zhimin Zhang; Xiaowei Li)
Abstract	With leakage power being no longer negligible, it becomes a critical problem for low power design. Input vector control is an effective method to reduce leakage power when a circuit enters sleep mode. It seeks to find a vector that minimizes leakage power to be statically applied to the primary inputs of a circuit. In this paper, we present a fast algorithm to search the input vector which can lead to the minimal leakage power. In order to accelerate the evaluation procedure, the circuit under simulation is reduced by circuit partition based on the level number of circuits first. Then, a searching algorithm based on sub-circuit is used to find the target input vector. Experimental results on combinational circuits of ISCAS85 benchmark show this algorithm can accelerate calculation over 5 times.
Starting Page	14
Ending Page	18
File Size	676450
Page Count	5
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611259
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage Circuit simulation Leakage current Partitioning algorithms Acceleration Power dissipation Combinational circuits Dynamic voltage scaling Registers Stacking gate-level simulator leakage power input vector control low power design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in