NDLI: Processor design considerations for wireless sensor network

Content Provider	IEEE Xplore Digital Library
Author	Yongjun Xu Lingyi Liu Peifu Shen Tao Lv Xiaowei Li
Copyright Year	2005
Description	Author affiliation: Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China (Yongjun Xu; Lingyi Liu; Peifu Shen; Tao Lv; Xiaowei Li)
Abstract	Wireless sensor networks are task-based networks, which have become one of the hottest research and application areas and already enabled numerous embedded wireless applications such as military, environmental monitoring, intelligent building etc. Low power design is an important topic of wireless sensor network. In this paper, a low-power processor (WO-LPP) is presented for WSN. Our processor has 8-bit simple 3-stage pipeline even-driven RISC ISA core with on-chip program flash and internal SRAM. At the same time, on-chip even-based task management, on-chip hardware management and power management scheme are coordinately designed with some general peripheral devices to meet most application environments. An AES (advanced encryption standard) engine is also designed. Application results show the processor is specially optimized for wireless sensor network.
Starting Page	212
Ending Page	214
File Size	2533852
Page Count	3
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611298
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design Wireless sensor networks Energy management Environmental management Monitoring Intelligent networks Intelligent sensors Intelligent structures Buildings Pipelines
Content Type	Text
Resource Type	Article

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