NDLI: Performance exploration and optimization of SDRAM-controller architecture on SDRAM access

Content Provider	IEEE Xplore Digital Library
Author	Zhang Yu Ling Ming Pu Hanlai Zhou Fan
Copyright Year	2005
Description	Author affiliation: Nat. ASIC Syst. Eng. Technol. Res. Center, Southeast Univ., Nanjing (Zhang Yu; Ling Ming; Pu Hanlai; Zhou Fan)
Abstract	The access operation between CPU and off-chip memory, such as SDRAM, is very frequent in embedded system. This being the case, we try to take full advantage of SDRAM by developing a novel SDRAM-controller architecture. The architecture is based on the SDRAM characteristics with full instruction flow analysis. Three techniques are employed for auto adaptive prefetch instruction, overlapping read latency, locality of reference and reduction of row miss mainly aroused by accessing stack data. The results using benchmark programs show that developed architecture reduce the memory latency by 71% on average
Starting Page	203
Ending Page	207
File Size	1552300
Page Count	5
File Format	PDF
ISBN	0780392108
DOI	10.1109/ICASIC.2005.1611296
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SDRAM Delay Embedded system Application specific integrated circuits Systems engineering and theory Content addressable storage Central Processing Unit Prefetching Memory architecture High performance computing instruction flow row miss row hit
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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