NDLI: A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

Content Provider	Directory of Open Access Journals (DOAJ)
Author	Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Jae Jin Lee Seong Jin Oh Younggun Pu Kang-Yoon Lee
Abstract	This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on $0.18~\mu \text{m}$ CMOS technology with an operational range of 350~900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 $mm^{2}$.
e-ISSN	21693536
DOI	10.1109/ACCESS.2020.2982180
Journal	IEEE Access
Volume Number	8
Language	English
Publisher	IEEE
Publisher Date	2020-01-01
Publisher Place	United States
Access Restriction	Open
Subject Keyword	Electrical Engineering. Electronics. Nuclear Engineering All Digital Delay Locked Loop (addll) Digital Controller Jitter Light Detection and Ranging (lidar) Time To Digital Converter (tdc)
Content Type	Text
Resource Type	Article

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