NDLI: Efficient VLSI architectures for a high-performance digital image communication system

Content Provider	IEEE Xplore Digital Library
Author	Lee, C.-Y. Catthoor, F. De Man, H.J.
Copyright Year	1983
Abstract	A typical digital image communication system based on a number of ASIC architectural designs is currently under development. After partitioning the complete system into several stages, each selected algorithm can be implemented on a single ASIC based on an efficient architectural style. The required throughput for high-performance data compression and channel coding has been obtained due to the optimization of the critical path in the architectural design. Input/output (I/O) operations, which create the bottleneck for many image-processing algorithms, are handled by a dedicated I/O interface unit. Construction of each dedicated data path in the architecture is based on a limited parameterizable functional building block (FBB) library. The dedicated data paths have been constructed by partitioning the initial signal flow graph (SFG) into compatible graphs and by matching the graphs in each partition onto a collection of time-multiplexed FBBs. Hierarchically partitioned controllers were used to meet the high-throughput requirements. The ASIC architectures proposed are oriented to broadband integrated services digital networks (B-ISDN) as well as high-performance digital image compression systems.<>
Starting Page	1481
Ending Page	1491
Page Count	11
File Size	1237683
File Format	PDF
ISSN	07338716
Volume Number	8
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Digital images Application specific integrated circuits Partitioning algorithms B-ISDN Throughput Data compression Channel coding Design optimization Libraries
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

New VLSI ASIC set for digital TV coding

A fast and area-efficient VLSI architecture for embedded image coding

VLSI video codec using programmable DSP

A complete VLSI treatment for the LAPD protocol (ISDN level 2)

ISDN-Oriented Modular VLSI Chip Set for Central-Office and PABX Applications

Cell Merge: A basic-pre-clustering clustering algorithm for placement

VLSI implementation of a color map inversion algorithm [color printer applications]

ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

VLSI architectures for digital image coding

Efficient VLSI architectures for a high-performance digital image communication system

Similar Documents

New VLSI ASIC set for digital TV coding

A fast and area-efficient VLSI architecture for embedded image coding

VLSI video codec using programmable DSP

A complete VLSI treatment for the LAPD protocol (ISDN level 2)

ISDN-Oriented Modular VLSI Chip Set for Central-Office and PABX Applications

Cell Merge: A basic-pre-clustering clustering algorithm for placement

VLSI implementation of a color map inversion algorithm [color printer applications]

ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

VLSI architectures for digital image coding

Efficient VLSI architectures for a high-performance digital image communication system