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Designing a time predictable memory hierarchy for single-path code
| Content Provider | ACM Digital Library |
|---|---|
| Author | Cilku, Bekim Puschner, Peter |
| Abstract | Trustable Worst-Case Execution-Time (WCET) bounds are a necessary component for the construction and verification of hard real-time computer systems. Deriving such bounds for contemporary hardware/software systems is a complex task. The single-path conversion overcomes this difficulty by transforming all unpredictable branch alternatives in the code to a sequential code structure with a single execution trace. However, the simpler code structure and analysis of single-path code comes at the cost of a longer execution time. In this paper we address the problem of the execu- tion performance of single-path code. We propose a new instuction-prefetch scheme and cache organization that uti- lize the \knowledge of the future" properties of single-path code to reduce the main memory access latency and the number of cache misses, thus speeding up the execution of single-path programs. |
| Starting Page | 16 |
| Ending Page | 21 |
| Page Count | 6 |
| File Format | |
| ISSN | 15513688 |
| DOI | 10.1145/2782753.2782755 |
| Journal | ACM SIGBED Review (SIGBED) |
| Volume Number | 12 |
| Issue Number | 2 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2004-10-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Memory hierarchy Prefetching Cache memories Hard real-time systems Time predictability |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Science 1700/1701 Engineering 2200/2201 |
