NDLI: Reduced switching mode for SAR ADCs: analysis and design of SAR A-to-D algorithm with periodic standby mode circuit components

Content Provider	IET Digital Library
Author	Joshi, Ashish Shrimali, Hitesh Sharma, Satinder K.
Abstract	This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue-to-digital (A-to-D) algorithm. For given analogue-to-digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching activity between the two samples can be eliminated by enabling periodic temporal reference to the converter. No prediction or logic circuitry is required to extract information from previous bits. However, there exists a trade-off between the input frequency and the sampling frequency. A design criterion is derived using numerical mathematics to skip evaluation of the optimum number of bits while maintaining the desired signal-to-noise and distortion ratio. The design criterion is validated through behavioural simulations using MATLAB/Simulink®. Furthermore, a fully differential 10-bit, 104 kS/s ADC is designed in a standard 180 nm CMOS technology to demonstrate circuit implementation of the RSw mode. In the RSw mode, power dissipation in the comparator and relevant digital circuitry decreases by 20%. The ADC achieves low-frequency effective number of bits of 9.7 bits and spurious free dynamic range of 68.3 dB. With 1.8 V supply voltage, average power dissipation in the core ADC is 2.54 μW; resulting in figure-of-merit of 29.3 fJ/conv-step.
Starting Page	686
Ending Page	694
Page Count	9
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 5, Aug (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0224
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-03-10
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Analogue-Digital Conversion Analogue-to-digital Converter Specifications Behavioural Simulations CMOS Digital Integrated Circuit CMOS Integrated Circuit Core ADC Design Criterion Digital Circuit Design, Modelling And Testing Digital Circuitry Dispensable Switching Activity Fully Differential ADC Input Frequency Integrated Circuit Design Layout Low Power Electronics MATLAB Simulink Environment Modelling And Testing Numerical Mathematics Periodic Standby Mode Circuit Component Periodic Temporal Reference Reduced Switching Activity Mode Successive Approximation Register Analogue-to-digital Algorithm RSw Mode Design Sampling Frequency SAR A-to-D Algorithm Semiconductor Integrated Circuit Design Signal Variation Signal-to-noise And Distortion Ratio Size 180 Nm Standard CMOS Technology Switching Mode Voltage 1.8 V Word Length 10 Bit Word Length 9.7 Bit
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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