NDLI: Exploiting uncertain timing information in time-based SAR ADCs

Content Provider	IET Digital Library
Author	Wang, Haibo Nagabhushana, Abhilash Karnatakam Leitner, Stefan
Abstract	Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.
Starting Page	390
Ending Page	397
Page Count	8
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 3, May (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0165
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-01-28
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor ADC Conversion Process ADC Input ADC SNDR Analogue-Digital Conversion Bit Information CMOS Digital Integrated Circuit CMOS Integrated Circuit CMOS Technology Delay Line Integrated Circuit Design Intermediate Stage Signal Layout Modelling And Testing Multistage VCDL Multistage Voltage Controlled Delay Line Pulse Circuit Semiconductor Integrated Circuit Design Signal-to-noise Distortion Ratio Silicon Measurement Size 130 Nm Time Conversion Time-based SAR ADC Time-based Successive Approximation Register Analogue-to-digital Converter Ultra-low Voltage Circuit Design Uncertain Timing Information Uncertainty-tolerant SAR Procedure VCDL Intermediate Stages Voltage 0.4 V Voltage Signal Word Length 9 Bit
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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