NDLI: Low-power successive approximation ADC using split-monotonic capacitive DAC

Content Provider	IET Digital Library
Author	Shakibaee, Fatemeh Sajedi, Fereshteh Saberi, Mehdi
Abstract	A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy capacitor switching technique is proposed which consumes no switching energy during the first three comparison steps. Moreover, an energy-efficient split-monotonic technique is utilised for the rest of the operations. Compared with the capacitor switching technique used in the conventional SA-ADC, the proposed scheme not only reduces the switching energy by 99.23% but also it has lowered the total capacitor size by 75%. Furthermore, in order to realise the proposed capacitor switching scheme, a power-efficient logic circuit is designed which reduces the power consumption of the required control logic circuit by reducing the activity of the employed D-type flip-flops. Based on the proposed scheme, a 10 bit 40 kS/s SA-ADC has been designed and simulated in a 0.18 µm complementary metal-oxide semiconductor technology with a supply voltage of 1 V. Post-layout simulation results show that the proposed ADC circuit achieves a signal-to-noise-and-distortion ratio of 60.8 dB at the cost of 270 nW power consumption, resulting in a figure-of-merit of 7.6 fJ/conversion step.
Starting Page	203
Ending Page	208
Page Count	6
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 2, Mar (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2017.0373
Journal	IET Circuits, Devices & Systems
Publisher Date	2017-10-27
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Analogue-Digital Conversion Capacitor Switching CMOS Integrated Circuit CMOS Logic Circuit CMOS Technology Control Logic Circuit D-type Flip-flop DAC Digital Circuit Design, Modelling And Testing Digital-analogue Conversion Energy Consumption Energy Efficient Split-monotonic Capacitive Digital-to-analogue Converter Flip Flops Integrated Circuit Layout Layout Logic And Switching Circuit Logic Circuit Logic Design Method Low Power Electronics Low Power-efficient Successive Approximation Analogue-to-digital Converter Low-energy Capacitor Switching Technique Modelling And Testing Noise Figure 60.8 DB Post-layout Simulation Power 270 NW Power Consumption Power Efficient Logic Circuit Design SA-ADC Semiconductor Integrated Circuit Design Signal-to-noise-and-distortion Ratio Size 0.18 Mum Voltage 1 V Word Length 10 Bit
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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