NDLI: Meta-stability immunity technique for high speed SAR ADCs

Content Provider	IET Digital Library
Author	Qiu, L. Tang, K. Zheng, Y. J. Siek, L.
Abstract	An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.
Starting Page	300
Ending Page	302
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 5, Mar (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.4001
Journal	Electronics Letters
Publisher Date	2017-02-06
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Analogue-Digital Conversion Analogue-to-digital Converter Circuit Stability CMOS Integrated Circuit CMOS Technology Effective Number of Bits ENOB High Speed SAR ADC Integrated Circuit Design Layout Metastability Immunity Technique Modelling And Testing Power 48 MW Semiconductor Integrated Circuit Design Size 65 Nm Storage Capacity 7.45 Bit Time-interleaved Successive Approximation Register Word Length 8 Bit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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