NDLI: Noise-power-area optimised design procedure for OTAs with complementary input transistors for neural amplifiers

Content Provider	IET Digital Library
Author	Das, Devarshi Mrinal Barot, Kashyap Srivastava, Abhishek Baghini, Maryam Shojaei
Abstract	Simultaneous measurement of neural bio-potentials from a large number of neurons is finding applications in a diverse range of areas such as healthcare and brain-machine interfacing. Neural amplifiers used for these measurements have a tight specification of low-power, low-noise and small area. Most of the reported neural amplifiers use operational transconductance amplifier (OTA) based capacitive feedback amplifiers to meet these requirements. In this study, for the first time, a novel systematic noise-power-area optimised design procedure, for complementary input transistor based OTAs, used frequently in neural amplifiers is proposed. By applying the proposed design procedure, the authors have presented a neural amplifier design that is split into two stages to reduce area requirement and enhance linearity at the expense of slight degradation in noise efficiency factor. The presented design achieves 2.1 μ V rms noise in the integration bandwidth of 0.2 Hz–8 kHz with 7.7 μA total current in a die area of 355 μ m × 175 μ m in 180 nm CMOS technology. The presented design procedure is inherently technology agnostic. The novelty lies not in the architecture of the proposed neural amplifier, but in the proposed design procedure to optimise the noise-power-area trade-off in CMOS amplifier circuit design.
Starting Page	702
Ending Page	706
Page Count	5
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 5, Aug (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0259
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-03-10
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Analogue Circuit Design Area Requirement Bandwidth 0.2 KHz to 8.0 KHz Circuit Implementations CMOS Amplifier Circuit Design CMOS Analogue Integrated Circuit CMOS Integrated Circuit Complementary Input Transistor Based OTAs Current 7.7 MuA Die Area Feedback Amplifiers Integrated Circuit Design Layout Low Power Electronics Low-noise Amplifier Modelling Modelling And Testing Neural Amplifier Design Neural Bio-potential Measurement Neural Chips Neural Nets Noise Efficiency Factor Noise-power-area Trade-off Noise-power-area Trade-off Optimization Operational Amplifier OTA Based Capacitive Feedback Amplifiers Semiconductor Integrated Circuit Design Size 180 Nm Size 355.0 Mum Systematic Noise-power-area Optimised Design Procedure Testing Transistor Circuit
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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