NDLI: Power-efficient flash ADC with complementary voltage-to-time converter

Content Provider	IET Digital Library
Author	Oh, D. R. Jo, D. S. Moon, K. J. Roh, Y. J. Ryu, S. T.
Abstract	A power-efficient complementary voltage-to-time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time-interleaved manner, resulting in significant power saving. A 5-bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage-to-time conversion-based flash ADC.
Starting Page	772
Ending Page	773
Page Count	2
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 12, Jun (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/12
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2017.1287
Journal	Electronics Letters
Publisher Date	2017-05-12
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Alternating Reset Direction Analogue-Digital Conversion CMOS Integrated Circuit CMOS Logic Circuit CMOS Process CVTC Integrated Circuit Design Layout Logic And Switching Circuit Logic Circuit Modelling And Testing Power Consumption Power Converter Power Electronics Power Supply Power-efficient Complementary Voltage-to-time Converter Power-efficient Flash ADC Semiconductor Integrated Circuit Design Signal Development Direction Size 40 Nm Supervisory Circuit Word Length 5 Bit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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