NDLI: Methodology and comparative design of an efficient 4-bit encoder with bubble error corrector for 1-GSPS flash type ADC

Content Provider	IET Digital Library
Author	Hussain, Sarfraz Kumar, Rajesh Trivedi, Gaurav
Abstract	The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm2.
Starting Page	629
Ending Page	639
Page Count	11
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 5, Aug (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0499
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-03-03
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	1-GSPS Flash Type ADC 4-bit Encoder A/D And D/A Convertor Analogue-Digital Conversion BEC Binary Codes Binary Encoder Bubble Error Correction Bubble Error Corrector Code Digital Circuit Design, Modelling And Testing Encoding Energy 3.335 FJ Error Correction Fat-Tree Encoder Flash Analogue-to-digital Converter Higher Order Bubble Correction Logic Design Method NAND Gate OR Gate Power 18.3563 PW Power 87.071 MuW Tree Code Voltage 1.8 V
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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