NDLI: Low-power time-based ADC with alternating time-residue amplification

Content Provider	IET Digital Library
Author	Jung, J. Shin, S.
Abstract	A time-based analogue-to-digital converter (ADC) that can exhibit both low power and high resolution is introduced. By amplifying alternate time residues and successively subtracting the comparator-induced timing offset, both fast conversion speed of 2N cycles for an N-bit converter and very small input-referred timing offset are achieved. For a 12-bit ADC implemented in a 0.18 µm CMOS process, an effective number of bits of 10.8 has been measured at a sampling frequency of 100 kHz, while consuming 30 µW of total power.
Starting Page	1845
Ending Page	1847
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 22, Oct (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/22
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.0831
Journal	Electronics Letters
Publisher Date	2016-10-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Alternating Time-residue Amplification Analogue-Digital Conversion Analogue-to-digital Converter CMOS Digital Integrated Circuit CMOS Integrated Circuit CMOS Process Comparator-induced Timing Offset Frequency 100 KHz Low Power Electronics Low-power Time-based ADC N-bit Converter Power 30 MuW Size 0.18 Mum Time Residues Word Length 12 Bit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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Low-power time-based ADC with alternating time-residue amplification