NDLI: Backplane bus controller implementation in Fpga for hard real time control systems

Content Provider	IEEE Xplore Digital Library
Author	Abbas, G.G. Yian Zhu Muhammad, A.H. Waqar, A. Jianfeng An
Copyright Year	2011
Description	Author affiliation: School of Computer Science and Technology, Northwestern Polytechnical University, 710072, Xi'an, China (Abbas, G.G.; Yian Zhu; Muhammad, A.H.; Waqar, A.; Jianfeng An)
Abstract	Aircraft information management system (AIMS) requires a highly reliable backplane bus protocol for the communication between its line replaceable units (LRU) to ensure the safety critical hard real time control system operation. As the time driven protocol is more reliable than the event driven protocols, this backplane bus needs to be implemented with time division control protocol. For that matter, more attention is needed to ensure the synchronization issues between LRUs. This paper addresses the controller implementation for bus interface unit (BIU) for the ARINC 659 backplane bus as an example, which controls all the BIU operations. This controller needs to fetch the commands from the table memory, decode them and then execute them to drive the bus for the BIU operations including message operations and synchronization handling. We have designed the Instruction Set Architecture (ISA) for table commands and implemented three Finite State Machines (FSM) for designing this controller along with some glue logic. First FSM is meant for managing commands, second for managing the BIU current state for synchronization needs, and the third for controlling the BIU operations. The aforesaid design has been modeled by using Verilog, Hardware Descriptive Language (HDL) and implemented in Altera Cyclone II board. Results of Modelsim and Quartus proved the cycle accurate implementation of controller in compliance with ARINC 659 specifications.
Starting Page	451
Ending Page	456
File Size	3803687
Page Count	6
File Format	PDF
ISBN	9781612844855
e-ISBN	9781612844862
DOI	10.1109/ICCSN.2011.6013870
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	AIMS Atmospheric modeling Hard Real Time control system FPGA ARINC 659 Backplane bus controller Educational institutions Synchronization Hardware design languages Oscillators
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA based real time implementation scheme for ARINC 659 backplane data bus

Implementation of data transfer and synchronous pulse operation for ARINC 659

Design and Implementation of Programmable Sequence Controller Based on FPGA

Implementation of ARINC 659 Bus Controller for Space-Borne Computers

Synchronization algorithm and FPGA implementation for Transmit-Reference UWB receiver

Design and application of portable test system of aero electronic equipment

Design of underwater robot controller based on CAN bus

Design and implementation of online fuzzy logic controller on FPGA

Design of dual redundancy CAN-bus controller based on FPGA

Backplane bus controller implementation in Fpga for hard real time control systems

Similar Documents

FPGA based real time implementation scheme for ARINC 659 backplane data bus

Implementation of data transfer and synchronous pulse operation for ARINC 659

Design and Implementation of Programmable Sequence Controller Based on FPGA

Implementation of ARINC 659 Bus Controller for Space-Borne Computers

Synchronization algorithm and FPGA implementation for Transmit-Reference UWB receiver

Design and application of portable test system of aero electronic equipment

Design of underwater robot controller based on CAN bus

Design and implementation of online fuzzy logic controller on FPGA

Design of dual redundancy CAN-bus controller based on FPGA

Backplane bus controller implementation in Fpga for hard real time control systems