NDLI: Verification and validation of UML 2.0 sequence diagrams using colored Petri nets

Content Provider	IEEE Xplore Digital Library
Author	Mozaffari, M. Harounabadi, A.
Copyright Year	2011
Description	Author affiliation: Islamic Azad University Tehran center Branch, Tehran, Iran (Harounabadi, A.) \|\| Islamic Azad University Arak Branch, Arak, Iran (Mozaffari, M.)
Abstract	One of the major challenges in the software development process is the improvement of the error detection in the early phases of the software life cycle. If the software error is detected at the design phase before of the implementation, the software quality will acceptably be increased. For this purpose, the Verification and Validation of UML diagrams play a very important role in detecting flaws at the design phase. This paper presents a Verification and Validation technique for one of the most popular UML diagrams: sequence diagrams. The proposed approach creates an executable model from UML interactions expressed in sequence diagrams using colored petri nets and uses CPN Tools to simulate the execution and to verify properties written in standard ML. In The proposed approach, we have used the sequence diagram elements including massages, send/receive events and source/destination of messages and have written properties in terms of boolean expression over the elements. The main contribution of this work is to provide an efficient mechanism to be able to track the execution state of an interaction in sequence diagram. The obtained results show that The proposed approach reduces impressively the probability of errors appearance at the software implementation phase. therefore, sofware can be more reliable at the end of the software development process.
Starting Page	117
Ending Page	121
File Size	199096
Page Count	5
File Format	PDF
ISBN	9781612844855
e-ISBN	9781612844862
DOI	10.1109/ICCSN.2011.6013675
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Computational modeling Unified modeling language Petri nets UML Receivers Programming Software colored petri nets verification and validation sequence diagram executable model
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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