NDLI: Static and dynamic energy losses vs. temperature in different CMOS technologies

Content Provider	IEEE Xplore Digital Library
Author	Kocanda, P. Kos, A.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron., AGH Univ. of Sci. & Technol., Krakow, Poland (Kocanda, P.; Kos, A.)
Abstract	The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of control signals a special testing circuit was designed. Change of dynamic energy, as a function of temperature, regardless of supply voltage fits in range of -0.5-7.3%. Static power dissipation, a result of existing leakage currents, rises with temperature. When temperature rises from 20 to 100°C static power multiplicities at least 3 times up to 85 times. When operating with low activity static energy consumptions has higher impact on total energy consumption. In most cases one cannot ignore temperature influence on energy consumption.
Starting Page	446
Ending Page	449
File Size	1474508
Page Count	4
File Format	PDF
e-ISBN	9788363578077
DOI	10.1109/MIXDES.2015.7208560
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-25
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Department of Microelectronics and Computer Science, Lodz Univeristy of Technology
Subject Keyword	Energy consumption Energy loss static and dynamic energy losses dynamic voltage scaling CMOS technology scaling Logic gates temperature dependence Inverters CMOS integrated circuits Transistors
Content Type	Text
Resource Type	Article

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