NDLI: Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications

Content Provider	IEEE Xplore Digital Library
Author	Halauko, A. Borejko, T. Pleskacz, W.A.
Copyright Year	2015
Description	Author affiliation: Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland (Halauko, A.; Borejko, T.; Pleskacz, W.A.)
Abstract	In this paper a comparison of four low noise amplifiers (LNAs), designed in fully depleted SOI 28 nm technology, has been presented. The objective of the presented work was to verify the usability of all kinds of MOSFET transistors that are available in UTBB for RF analog designs. The inductively degenerated cascodes were used in simulations. Such topology achieves high gain and low noise figure (NF). Simulated amplifiers were designed for a high sensitivity GNSS receiver, which operates in the Galileo/GPS E1/L1 band. The implemented circuits demonstrate the gain of 22.3 dB and the consumption current of 2.5 mA, with NF equal to 1.92 dB. For all amplifiers the supply voltage is 0.6 V and the silicon die estimated area is equal to 0.7 $mm^{2}.$
Starting Page	354
Ending Page	358
File Size	1004039
Page Count	5
File Format	PDF
e-ISBN	9788363578077
DOI	10.1109/MIXDES.2015.7208542
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-25
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Department of Microelectronics and Computer Science, Lodz Univeristy of Technology
Subject Keyword	MOSFET GNSS RFIC wearables GPS Global Positioning System IoT CMOS Impedance matching RF FDSOI UTBB NF CMOS integrated circuits Impedance Galileo Gain LNA back-gate
Content Type	Text
Resource Type	Article

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