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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mielczarek, A. Perek, P. Makowski, D. Napieralski, A. Sztoch, P. |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Microelectron. & Comput. Sci., Lodz Univ. of Technol., Lodz, Poland (Mielczarek, A.; Perek, P.; Makowski, D.; Napieralski, A.) || FINN Sp. z o. o., Lodz, Poland (Sztoch, P.) |
| Abstract | The paper presents a FPGA-based dedicated system for rapid calibration of 3D camera rigs. The developed device aims to help during camera set-up, by allowing the operator to easily compare the images from two cameras with use of several composition methods. The paper indicates the challenges related to development of high-throughput video processing systems in FPGA circuits. The processing methods were developed and verified using a platform with recent Kintex-7 FPGA device from Xilinx. The article covers the details of the implementation of the image analyser prototype. Moreover it identifies the crucial design considerations and addresses the problems that any FPGA designer can encounter during development of video processing systems. |
| Starting Page | 138 |
| Ending Page | 140 |
| File Size | 451016 |
| Page Count | 3 |
| File Format | |
| e-ISBN | 9788363578077 |
| DOI | 10.1109/MIXDES.2015.7208497 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-06-25 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Department of Microelectronics and Computer Science, Lodz Univeristy of Technology |
| Subject Keyword | Three-dimensional displays camera rig calibration Stereo image processing 3D cinema Streaming media Cameras stereoscopic video processor Calibration Mirrors Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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