NDLI: Area-saving technique for low-error redundant binary fixed-width multiplier implementation

Content Provider	IEEE Xplore Digital Library
Author	Tso-Bing Juang Chi-Chung Wei Chip-Hong Chang
Copyright Year	2009
Description	Author affiliation: Department of CSIE, National Pingtung Institute of Commerce, Taiwan (Tso-Bing Juang; Chi-Chung Wei) \|\| School of Electrical, Electronic Engineering, Nanyang Technological University, Singapore (Chip-Hong Chang)
Abstract	A recently proposed architecture of redundant binary fixed-width multiplier was shown to outperform several normal binary fixed-width multipliers in terms of accuracy. However, its merit due to the carry-free addition property of the binary signed digit (BSD) partial products has been offset by the high area overhead of the redundant binary full adder tree. To achieve low-error fixed-width multiplication with smaller silicon area, we propose a hybrid structure which makes use of dual polarity high order column compressors and (3:2) counters to parallelly reduce the positive and negative BSD partial products. Our proposed technique has led to a fixed-width multiplier architecture with the same accuracy and up to 42% area saving for 10×10-bit multiplication over the conventional redundant binary fixed-width multiplier architecture in 0.18 □m CMOS standard cell implementation under the same timing constraint.
Starting Page	550
Ending Page	553
File Size	403116
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	Fixed-width multipliers Error compensation Dynamic range Compressors Counting circuits redundant binary signed digit representation Cities and towns Silicon Timing modified Booth encoding Finite wordlength effects Adders Business
Content Type	Text
Resource Type	Article

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