NDLI: A pseudo fractional-n and multiplier clock generator with 50% duty cycle output using low power phase combination controller

Content Provider	IEEE Xplore Digital Library
Author	Wan-Lun Gao Wei-Bin Yang Yu-Lung Lo
Copyright Year	2009
Description	Author affiliation: dept. of Electronic Engineering, National Kaohsiung Normal University, Taiwan, R.O.C. (Yu-Lung Lo) \|\| dept. of Electrical Engineering, Tamkang University, Taipei, Taiwan R.O.C. (Wan-Lun Gao; Wei-Bin Yang)
Abstract	Because system-on-a-chip (SOC) needs multiple clocks and mostly with 50% duty cycle in the same chip, in this paper, the new pseudo fractional-N and multiplier clock generator with low power phase combination controller and 50% duty cycle is proposed to achieve this purpose. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed fractional-N or multiplier clock frequencies with 50% duty cycle. Furthermore, the frequency of the output clock can be programmed by the low power phase combination controller. The circuits are processed in a standard 0.35µm CMOS technology, and work with a supply voltage of 3.3V. The simulation results demonstrate that the low power phase combination controller can save power dissipation from 9.7%∼22.9%.
Starting Page	562
Ending Page	565
File Size	531004
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	Voltage-controlled oscillators Circuits fractional Frequency CMOS technology Control systems CMOS process clock System-on-a-chip Phase locked loops Power generation Clocks
Content Type	Text
Resource Type	Article

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