NDLI: New look-up-table optimizations for memory-based multiplication

Content Provider	IEEE Xplore Digital Library
Author	Meher, P.K.
Copyright Year	2009
Description	Author affiliation: Communication Systems Department, Institute for Infocomm Research, 1 Fusionopolis Way, Singapore (Meher, P.K.)
Abstract	Two new techniques are presented in this paper, for the reduction of look-up-table (LUT) size of memory-based multipliers to be used in digital signal processing applications. It is shown that by simple sign-bit exclusion, the LUT size is reduced by half at the cost of a marginal area overhead. Moreover, a novel anti-symmetric product coding (APC) scheme is proposed to reduce the LUT size by further half, where the LUT output is added with or subtracted from a fixed value. It is shown that the optimized LUTs for small input width could be used for efficient implementation of high-precision LUT-multipliers, where the total contribution of all such fixed offsets could be added to the final result or could be initialized for successive accumulations. The proposed LUT-multiplier and the existing ones are coded in VHDL and synthesized by Synopsys Design Compiler using TSMC 90 nanometer library. The proposed optimized LUT-multiplier is found to involve less area and less multiplication time than the existing LUT-multipliers. The conventional LUT-multiplier and the odd-multiple storage LUT of [1] involve nearly 56.8% and 26.2% more area-delay product, in average, for 16-bit input than the proposed LUT design.
Starting Page	663
Ending Page	666
File Size	375036
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	Energy consumption Costs Signal processing algorithms Digital signal processing Libraries Table lookup Size control Logic Digital filters Semiconductor memory
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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