NDLI: Temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture

Content Provider	IEEE Xplore Digital Library
Author	Chongyong Yin Shouyi Yin Leibo Liu Shaojun Wei
Copyright Year	2009
Description	Author affiliation: Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing, China (Chongyong Yin; Shouyi Yin; Leibo Liu; Shaojun Wei)
Abstract	A temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture is presented to improve system's performance for satisfying the constraints of application parts executed on the reconfigurable hardware. The input of algorithm is data-flow graph (DFG) created from partitioned source code which will be mapped on the reconfigurable hardware and the reconfigurable hardware description. The critical path and the mobility of each node are obtained by performing the as soon as possible (ASAP) and as late as possible (ALAP) scheduling algorithms. Then the partitioning phase based on the critical path is applied to maximize the operation parallelism and reduce the communication costs by scheduling the node among partitions. Experimental results show the number of partitions is a slight reduction, and the communication cost is dramatically reduced to other temporal partitioning algorithms.
Starting Page	659
Ending Page	662
File Size	424951
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	Laboratories Partitioning algorithms scheduling algorithm temporal partitioning Scheduling algorithm Microprocessors Clustering algorithms Computer architecture Parallel processing Cost function Hardware reconfigurable computing Kernel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Mapping Algorithm for Coarse-Grained Reconfigurable Multimedia Architectures

A Multipurpose Clustering Algorithm for Task Partitioning in Multicore Reconfigurable Systems

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures

A scalable scheduling algorithm for coarse-grained reconfigurable architecture

A novel scheduling algorithm for dynamically reconfigurable computing systems

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Scheduling Temporal Partitions in a Multiprocessing Paradigm for Reconfigurable Architectures

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

Integrated kernel partitioning and scheduling for coarse-grained reconfigurable arrays.

Temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture

Similar Documents

Mapping Algorithm for Coarse-Grained Reconfigurable Multimedia Architectures

A Multipurpose Clustering Algorithm for Task Partitioning in Multicore Reconfigurable Systems

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures

A scalable scheduling algorithm for coarse-grained reconfigurable architecture

A novel scheduling algorithm for dynamically reconfigurable computing systems

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Scheduling Temporal Partitions in a Multiprocessing Paradigm for Reconfigurable Architectures

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

Integrated kernel partitioning and scheduling for coarse-grained reconfigurable arrays.

Temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture