NDLI: A lightweight memory encryption cache design and implementation for embedded processor

Content Provider	IEEE Xplore Digital Library
Author	Zhenglin Liu Wenjie Huo Xuecheng Zou Yingyan Lin
Copyright Year	2009
Description	Author affiliation: Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, China (Zhenglin Liu; Wenjie Huo; Xuecheng Zou; Yingyan Lin)
Abstract	Memory encryption offers a secure protection for the confidentiality of program and data. But implementing an encryption design for embedded processor is much difficult. As the embedded processor is highly constrained by the application requirement, the designers can't only concern with security. This paper proposes a new lightweight memory encryption cache (MEC) to obtain a balance among the performance, the power and the security. The new cache uses an improved cache structure to cache the pad value and decrease the latency of encryption. Our experiments show that the MEC has an 8.24% performance improvement over the direct encryption scheme in best case, and reduces 25.71% power consumption when the embedded processor writes back to memory, as compared with the OTP (one-time-pad) scheme.
Starting Page	57
Ending Page	60
File Size	1116571
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	Process design Advanced Encryption Standard(AES) cache Data security Read-write memory embedded processor Power system security Delay Counting circuits Embedded system Information security memory encryption Cryptography Protection
Content Type	Text
Resource Type	Article

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