NDLI: A 1.8 V to 3.3 V level-converting flip-flop design for multiple power supply systems

Content Provider	IEEE Xplore Digital Library
Author	Chua-Chin Wang Jen-Wei Liu Ron-Chi Kuo Li, K.S.-M. Sying-Jyan Wang
Copyright Year	2009
Description	Author affiliation: Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan (Li, K.S.-M.) \|\| Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan (Chua-Chin Wang; Jen-Wei Liu; Ron-Chi Kuo) \|\| Department of Computer Science and Engineering, National Chung-Hsing University, Taichung, Taiwan (Sying-Jyan Wang)
Abstract	The voltage islands scheme using multiple supply voltages (MSV) has been widely used in system-on-chip (SOC) designs to reduce the unnecessary power dissipation in non-critical function blocks. In these SOC designs, the circuit blocks with the same voltage level are clustered into a single voltage island to reduce the cost of voltage supply network and the power consumption. However, a voltage level converter is required to stitch different voltage islands when the normal scan mode is activated. Besides carrying out the scan testing function, the level converter should be able to overcome the gate-oxide overstress problem given more than two supply voltages and backward compatibility. In this study, a 1.8 V to 3.3 V levelconverting flip-flop (LCFF) implemented using 0.18 µm CMOS technology is proposed. By utilizing the voltage keeper technique, the power consumption and the power delay product (PDP) can be successfully reduced without any leakage current path.
Starting Page	61
Ending Page	64
File Size	1136262
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	Energy consumption Costs Power supplies Dual-supply voltage level conversion Circuit testing Delay Flip-flops Voltage CMOS technology Power dissipation System-on-a-chip flip-flop
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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