NDLI: The new ATE: Protocol aware

Content Provider	IEEE Xplore Digital Library
Author	Evans, A.C.
Copyright Year	2007
Description	Author affiliation: Broadcom Corp., Irvine, CA (Evans, A.C.)
Abstract	Deep submicron shrinking IC geometries have enabled massive integration on an unprecedented level. Silicon companies with substantial IP libraries are able to manufacture a device that is a true "system " with diverse IP blocks in a single process on a single die. It is an ever increasing difficulty to adequately and cost effectively test a device at a "system level", let alone implement DFT for a "system " vs. a multitude of stand-alone IP blocks, each with their own test strategy. In the past 20 years, since the first mixed-signal or SOC ATE test systems appeared, there has not been any significant evolution in ATE architecture allowing for true system level test. This paper is a calling to automated test equipment suppliers (and silicon providers to help the call) to make a broad paradigm shift in ATE architecture that will enable true system level testing as part of the production test flow and methodology. ATE would be transformed from a simulation based environment to also include a real time protocol aware environment. Protocol aware ATE is possible, and it is drastically needed to achieve lowest possible defect rate, lowest cost, and fastest time to market for highly integrated semiconductors.
Starting Page	1
Ending Page	10
File Size	1972638
Page Count	10
File Format	PDF
ISBN	9781424411276
ISSN	10893539
DOI	10.1109/TEST.2007.4437617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols System testing Silicon Costs Automatic testing Geometry Libraries Manufacturing processes Test equipment Flow production systems
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Bridging the gap between embedded test and ATE

ATE and quality-an user's view

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Navigating test access in systems

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Low cost ATE pin electronics for multigigabit-per-second at-speed test

Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications

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The new ATE: Protocol aware

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