NDLI: Gate delay ratio model for unified path delay analysis

Content Provider	IEEE Xplore Digital Library
Author	Okuda, Y.
Copyright Year	2007
Description	Author affiliation: Sony Corp., Atsugi (Okuda, Y.)
Abstract	A new paradigm of path delay analysis is proposed against increasing process variation. A simple yet effective model - gate delay ratio model (GDRM) - is introduced to analyze the path delays of production devices without modifying device circuits and ATE systems. Curve fitting of the power voltage dependence of a delay on GDRM obtains the wire delay, gate delay, and threshold voltage of the transistors of the gates in a path. The new paradigm is verified by the evaluation of scan tests, SRAM MBISTs, ring oscillators, and SRAM test chips, which were fabricated by the 130, 90, and 65 nm devices of three companies. The analysis of parametric failures based on the proposal is demonstrated on thermal inversion failures. The verification and demonstration indicate the possibility of the new paradigm to coordinate design, manufacturing, characterization, and testing to reduce process variations and parametric defects.
Starting Page	1
Ending Page	10
File Size	678476
Page Count	10
File Format	PDF
ISBN	9781424411276
ISSN	10893539
DOI	10.1109/TEST.2007.4437592
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power system modeling Delay effects Threshold voltage Random access memory Production systems Curve fitting Wire Circuit testing Ring oscillators Failure analysis
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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