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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Seongmoon Wang Zhanglei Wang Wenlong Wei Chakradhar, S.T. |
| Copyright Year | 2007 |
| Description | Author affiliation: NEC Labs. America, Princeton, NJ (Seongmoon Wang) |
| Abstract | This paper presents a test data compression scheme that combines weighted random pattern testing and LFSR reseeding. Test patterns generated by the proposed decompressor can achieve high n-detection fault coverage. The proposed technique computes weight sets from a set of test cubes that are generated by a traditional 1-detection ATPG tool. The computed weight sets are modified to achieve high n-detection fault coverage. The proposed decompressor can be implemented with low area overhead. Since the proposed technique requires no special ATPG that is customized for the proposed scheme, it can compress test patterns generated by any ATPG tool and generate test patterns from the compressed test data that achieve high n-detection fault coverage. Experimental results show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits. |
| Starting Page | 1 |
| Ending Page | 10 |
| File Size | 387025 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781424411276 |
| ISSN | 10893539 |
| DOI | 10.1109/TEST.2007.4437612 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-21 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Test data compression Circuit faults Circuit testing Test pattern generators Automatic test pattern generation Automatic testing Fault detection National electric code System testing |
| Content Type | Text |
| Resource Type | Article |
| Subject | Applied Mathematics Electrical and Electronic Engineering |
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