NDLI: A fully digital-compatible BIST strategy for ADC linearity testing

Content Provider	IEEE Xplore Digital Library
Author	Hanqing Xing Hanjun Jiang Degang Chen Geiger, R.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA (Hanqing Xing)
Abstract	Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. On-chip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs' nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the $INL_{k}$ error of 12-bit ADCs to plusmn0.2 LSB accuracy level using only 7-bit linear DACs.
Starting Page	1
Ending Page	10
File Size	593221
Page Count	10
File Format	PDF
ISBN	9781424411276
ISSN	10893539
DOI	10.1109/TEST.2007.4437655
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Linearity Circuit testing System testing Costs Automatic testing Instruments Logic testing Signal generators Memory
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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