NDLI: Verification and debugging of I test of low power chips

Content Provider	IEEE Xplore Digital Library
Author	Laisne, M. Nguyen, T. Zuo, S. Pan, X. Cui, H. Bai, C. Street, A. Parley, M. Agrawal, N. Sundararaman, K.
Copyright Year	2007
Description	Author affiliation: Qualcomm Inc., San Diego, CA (Laisne, M.; Nguyen, T.; Zuo, S.; Pan, X.; Cui, H.; Bai, C.; Street, A.; Parley, M.; Agrawal, N.; Sundararaman, K.)
Abstract	Quiescent supply current $(I_{DDQ})$ is a very effective test method for CMOS circuits. However, $I_{DDQ}$ vector verification and debugging may take considerable time and effort; various problems have been encountered in this process, so different tools and methodologies have been devised to address them. For pre-silicon $I_{DDQ}$ vector verification, a modular approach is adopted. $I_{DDQ}$ is estimated for each vector based on leakage libraries of cells, and cell constraints can be verified automatically. For post-silicon $I_{DDQ}$ vector issues, methods and analysis tools have been developed to identify the root causes. Scan cell and net value analysis will identify critical scan cells and nets, which will determine whether an $I_{DDQ}$ pattern passes or fails, thus revealing the source of the extra leakage. These methodologies are proven to be very successful for $I_{DDQ}$ vector debug and $I_{DDQ}$ diagnosis.
Starting Page	1
Ending Page	7
File Size	466393
Page Count	7
File Format	PDF
ISBN	9781424411276
ISSN	10893539
DOI	10.1109/TEST.2007.4437628
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Debugging Circuit testing Power supplies Energy consumption Libraries Failure analysis Pattern analysis Geometry Sleep Current supplies
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in