NDLI: Protocol requirements in an SJTAG/IJTAG environment

Content Provider	IEEE Xplore Digital Library
Author	Carlsson, G. Holmqvist, J. Larsson, E.
Copyright Year	2007
Description	Author affiliation: Ericsson AB, Stockholm (Carlsson, G.)
Abstract	Integrated circuits, printed circuits boards, and multi-board systems are becoming increasingly complex to test. A major obstacle is test access, which would be eased by effective standards for the communication between devices-under-test (DUTs) and the test manager. Currently, the Internal Joint Test Access Group (IJTAG) work at micro-level on a standard for interfacing embedded on-chip instruments while the System JTAG (SJTAG) work at macro-level on a standard for system-level test management that connects IJTAG compatible instruments with the system test manager. In this paper we discuss requirements on a test protocol to be used in an SJTAG/ IJTAG environment. We have from a number of use scenarios made an analysis and defined protocol requirements. We have taken the Standard Test and Programming Language (STAPL), which is built around a player (interpreter), and defined required extensions. The extensions have been implemented in an extended version of STAPL and we have made experiments with a PC acting as test controller and an FPGA being the DUT.
Starting Page	1
Ending Page	9
File Size	307199
Page Count	9
File Format	PDF
ISBN	9781424411276
ISSN	10893539
DOI	10.1109/TEST.2007.4437658
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing System testing Access protocols Instruments Printed circuits Integrated circuit testing Communication standards System-on-a-chip Computer languages Field programmable gate arrays
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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