NDLI: Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors

Content Provider	IEEE Xplore Digital Library
Author	Machado Diniz, C. Beck Fonseca, M. Costa, E. Bampi, S.
Copyright Year	2015
Description	Author affiliation: Polytech. Inst., Catholic Univ. of Pelotas (UCPel), Pelotas, Brazil (Machado Diniz, C.; Costa, E.) \|\| Inf. Inst., Fed. Univ. of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil (Bampi, S.) \|\| Eng. Center, Fed. Univ. of Pelotas (UFPel), Pelotas, Brazil (Beck Fonseca, M.)
Abstract	The recent High Efficient Video Coding (HEVC) standard introduces a new and complex interpolation filter for fractional-pixel motion estimation. Recent works propose hardware architectures to accelerate the interpolation filter, employing interpolation datapaths with many adders in parallel. Adder compressors are area- and power-efficient operators that are applied when intermediate additions are not required, which is the case for interpolation filters. This work employs various hierarchical adder compressor structures in the interpolation filter datapaths of a state-of-the-art HEVC interpolation filter architecture. Hardware design results show that datapaths using adder compressors reduce power by up to 15% and power delay product by up to 30% compared to the same filters with ripple-carry adders.
Starting Page	1
Ending Page	4
File Size	285422
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7182087
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Adders Compressors Interpolation Computer architecture Video coding Hardware Acceleration Adder compressors Video Coding Hardware Architecture VLSI Design
Content Type	Text
Resource Type	Article

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