NDLI: Considerations for high-speed configurable-bandwidth time-interleaved digital delta-sigma modulators and synthesis in 28 nm UTBB FDSOI

Content Provider	IEEE Xplore Digital Library
Author	Marin, R.-C. Frappe, A. Kaiser, A. Cathelin, A.
Copyright Year	2015
Description	Author affiliation: STMicroelectron., Crolles, France (Cathelin, A.) \|\| IEMN-ISEN, Lille, France (Marin, R.-C.; Frappe, A.; Kaiser, A.)
Abstract	This paper presents the design and simulation of a time-interleaved delta-sigma modulator as part of a digital transmitter chain. The architecture is chosen based on a critical path analysis in order to reach very high frequency operation. The modulator's configurability allows it to target signal bandwidths from 20 MHz up to 160 MHz with a SNR greater than 67 dB. Finally, the modulator is synthesized using standard cells in 28nm FDSOI CMOS from STMicroelectronics and simulated for different numbers of time-interleaved channels, reaching a sample rate of up to 6 GS/s. An optimum number of channels can be found based on a trade-off between operating frequency, supply voltage, power consumption and area.
Starting Page	1
Ending Page	4
File Size	364115
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7182049
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency modulation Bandwidth Transmitters Power demand Delays Signal to noise ratio digital transmitter Delta Sigma Modulator (DSM) time-interleaving critical path analysis
Content Type	Text
Resource Type	Article

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