NDLI: Q-enhancement with on-chip inductor optimization for reconfigurable Δ-Σ radio-frequency ADC

Content Provider	IEEE Xplore Digital Library
Author	Lota, J. Demosthenous, A.
Copyright Year	2015
Description	Author affiliation: Sch. of Archit., Comput. & Eng., Univ. of East London, London, UK (Lota, J.) \|\| Dept. of Electron. & Electr. Eng., Univ. Coll. London, London, UK (Demosthenous, A.)
Abstract	The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissipation and dynamic element matching. System level simulations indicate at a Q-factor of 75 Δ-Σ modulator with a 3-level quantizer achieves dynamic ranges of 106, 82 dB and 84 dB for RFID, TETRA, and Galileo over bandwidths of 200 kHz, 10 MHz and 40 MHz respectively.
Starting Page	1
Ending Page	4
File Size	776697
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7182018
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inductors Radiofrequency identification Radio frequency Q-factor System-on-chip Frequency modulation on-chip inductor Q-enhancement RF delta-sigma
Content Type	Text
Resource Type	Article

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