NDLI: Application-specific shared last-level cache optimization for low-power embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Huatao Zhao Jiongyao Ye Xian Su Watanabe, T.
Copyright Year	2015
Description	Author affiliation: Grad. Sch. of IPS, Waseda Univ., Kitakyushu, Japan (Huatao Zhao; Jiongyao Ye; Xian Su; Watanabe, T.)
Abstract	Modern embedded systems favor the chip multiprocessor frame to achieve higher performance, but they are restricted by the inefficient cache hierarchies. Typically, the accessing interference and improper allocation in last-level cache (LLC) shared by multiprocessors cause significant energy consumption and performance depression. In this paper, we propose a configurable and partitioned cache hierarchy where an energy-efficient runtime mechanism can well manage the shared LLC to meet application programs. This mechanism utilizes the repeated behaviors in hot subroutines of application and selects the proper partition intervals. Then, a low-power metric based configurable scheme is employed to explore the optimal allocation of given cache resources. Thus, we can provide each core with the optimal allocation information to dynamically partition the shared LLC during runtime. Experimental results for a quad-core system using the SPEC2006 benchmarks show that the cache access energy can be reduced by on average 32.5 percent compared to the equal partition scheme only with 1.3 percent performance off.
Starting Page	1
Ending Page	4
File Size	154940
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7181994
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithms Runtime Embedded systems Resource management Benchmark testing Optimized production technology Interference
Content Type	Text
Resource Type	Article

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