NDLI: Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance

Content Provider	IEEE Xplore Digital Library
Author	Soares, L.B. Bampi, S. Rosa, A.L.R. Costa, E.A.C.
Copyright Year	2015
Description	Author affiliation: Grad. Program on Microelectron. (PGMicro), Porto Alegre, Brazil (Soares, L.B.; Bampi, S.) \|\| PPGC - Inf. Inst., Fed. Univ. of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil (Rosa, A.L.R.) \|\| Catholic Univ. of Pelotas (UCPEL), Porto Alegre, Brazil (Costa, E.A.C.)
Abstract	Near-threshold computing in CMOS is a promising alternative for any application which can tolerate very wide voltage-frequency scaling (VFS). Internet-of-Things (IoT) devices will operate in very different power-performance modes, from sub-MHz to peaks of hundreds of MHz. The nano-power range which is achievable in deca-nanometer CMOS at near-VT is the alternative we explore for VLSI circuits (8051 processor, filters, and ISCAS benchmark circuits). This paper proposes a method to design CMOS circuits for a wide dynamic range of VFS, and targets near-threshold for best efficiency. A standard-cell based design methodology specific for near-VT is demonstrated here in for a commercial 65nm CMOS process. Power and timing variability are characterized, so that variation-aware and yet ultra-low supply voltage designs are enabled. Our cell design method avoids unnecessary upsizing and it focus on near- and well above threshold regions of operation. For the study cases of medium complexity notch filter design (24kgates), and an 8051 compatible core (20kgates) we demonstrate 63X to 77X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from hundreds of KHz to 1GHz) in their operating modes. The results were obtained using the minimal cycle time achievable at each supply voltage. The extremely low and highly-variable performance at sub- and near-VT have to be addressed by new logic design paradigms. In this paper we also exploit the use of approximate adders to increase the timing performance of a class of digital filter circuits, to enable compensating the performance loss inherent to near-VT operation in CMOS. Our results show that the effort to explore energy savings in low power optimized circuits through the approximate computing approach is validated with energy and worst path delay reductions up to 19.4% and 36.7% respectively, compared to the precise arithmetic implementation, without compromising the filters frequency response. Our approximate adder method enables higher levels of energy efficiency in CMOS VLSI filters.
Starting Page	1
Ending Page	4
File Size	309311
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7182030
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filters Adders CMOS integrated circuits Libraries Approximation methods Energy efficiency Timing digital filters architectures energy efficiency near-threshold approximate computing VLSI design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI

Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling

High efficiency Biquad infinite impulse response filter using charge recovery logic family

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library

Low-energy digital filter design based on controlled timing error acceptance

Power analysis of multiplier blocks

Architectural synthesis of finite impulse response digital filters

A multi-output second-order digital filter structure for VLSI implementation

LMSGEN: a prototyping environment for programmable adaptive digital filters in VLSI

Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance

Similar Documents

Approximate adder synthesis for area- and energy-efficient FIR filters in CMOS VLSI

Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling

High efficiency Biquad infinite impulse response filter using charge recovery logic family

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library

Low-energy digital filter design based on controlled timing error acceptance

Power analysis of multiplier blocks

Architectural synthesis of finite impulse response digital filters

A multi-output second-order digital filter structure for VLSI implementation

LMSGEN: a prototyping environment for programmable adaptive digital filters in VLSI

Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance