NDLI: Modeling & PVT characterization of arbitrary ordered VSCP-PLL using an efficient event-driven approach

Content Provider	IEEE Xplore Digital Library
Author	Ali, E. Rahajandraibe, W. Tall, N. Haddad, F. Hangmann, C. Hedayat, C.
Copyright Year	2015
Description	Author affiliation: Dept. ASE, Fraunhofer ENAS, Paderborn, Germany (Hedayat, C.) \|\| IM2NP, Univ. of Aix-Marseille & Toulon, Marseille, France (Ali, E.; Rahajandraibe, W.; Tall, N.; Haddad, F.) \|\| Sensor Technol. Group, Univ. of Paderborn, Paderborn, Germany (Hangmann, C.)
Abstract	The charge-pump phase locked loop (CP-PLL) is a mostly used integrated circuit (IC) in various modern electronics applications to perform several functions. Due to its mixed analog and digital nature, often circuit level simulators are used to characterize its overall nonlinear dynamic behavior. Since the existing analytical methods are not efficient to account non-ideal and non-linear effects. Furthermore, considering a CP-PLL for frequency synthesis function, a low and high frequency part result in very long simulation times. Consequently, Spice like electrical simulator do not provide a quick assessment of the overall non-linear dynamic behavior of the CP-PLL. Additionally the PVT (Process, Voltage, and Temperature) variations are the most important aspect of the design flow to achieve a robust system. In this paper, a first ever PVT characterization of arbitrary ordered voltage switch charge pump PLLs (VSCP-PLL) designed at transistor level (TL) using 130nm CMOS process is presented. By extracting the macroscopic behavior and initial conditions, the simulations were performed using an efficient Event-Driven (ED) approach. The PVT characterization results of the ED-approach are very close to the TL-simulations with a good agreement in accuracy and speed-up factor of 60,000 &7,000 for $2^{nd}$ and $3^{rd}$ order PLL is achieved respectively.
Starting Page	1
Ending Page	4
File Size	373022
Page Count	4
File Format	PDF
ISBN	9781479988938
DOI	10.1109/NEWCAS.2015.7182081
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Voltage-controlled oscillators Switches Integrated circuit modeling Mathematical model Charge pumps Phase frequency detector PVT variations Charge-pump phase locked loop event-driven modeling technique transistor level simulations
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in